3D Semiconductor Memory Charge Storage Segmentation

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Solution Overview

Problem

Three-dimensional semiconductor memory devices face reliability issues due to charge movement and interface characteristics between different material layers, leading to decreased performance and durability.

Innovation Solution

A semiconductor device design featuring a channel layer with alternating protrusions and depressions, surrounded by a tunnel insulating layer, first and second charge storage patterns, and blocking insulation patterns, where the blocking insulation patterns are oxidized to prevent charge movement and separate the charge storage patterns, enhancing the structural integrity and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory cells are stacked in multiple layers to increase integration density, then the degree of integration is improved, but charge movement along the charge storage layer causes reliability deterioration

Engineering Contradiction:
Improveintegration densityVSAvoiddevice reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The charge storage layer is divided into multiple independent stacked layers, each capable of storing charges independently. This segmentation prevents charge movement between layers and allows each layer to function as a separate memory cell, resolving the reliability issue while maintaining high integration density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A blocking insulating layer is introduced between adjacent charge storage layers to act as an intermediary barrier. This blocking layer prevents charge movement and interaction between stacked charge storage layers, eliminating the harmful charge migration effect while enabling multi-layer stacking for high integration

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If charges are stored in portions of the charge storage layer at intersections with word lines, then memory cell functionality is achieved, but charge movement in the vertical direction deteriorates reliability

Engineering Contradiction:
Improvememory cell functionalityVSAvoidcharge storage stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The charge storage layer is segmented into multiple stacked independent layers, where each layer's charges are confined to its own layer. This prevents vertical charge movement between layers while maintaining the ability to store charges at word line intersections within each layer

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Blocking insulating layers are placed between adjacent charge storage layers to serve as intermediaries that block charge movement. This allows each charge storage layer to independently store charges at intersections with word lines without charge migration to adjacent layers, improving charge storage stability

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents undesirable charge-trapping interfaces and improves the reliability of three-dimensional semiconductor memory devices by structurally separating charge storage patterns and blocking insulation patterns, thereby enhancing the device's performance and durability.

Implementation Method 1

the blocking insulation patterns are oxidized to prevent charge movement and separate the charge storage patterns

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS9576977B2Semiconductor device and method of manufacturing the same
Publication Date: 2017.02.21 SK HYNIX INC
  • US9576977B2 patent drawing
  • US9576977B2 patent drawing
  • US9576977B2 patent drawing

AI summary

A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.