Active Pillar DRAM Structure With Concave-Convex Gate Control
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Solution Overview
Problem
As semiconductor devices scale down, the size of transistors decreases, leading to weakened gate control capability and a more pronounced short-channel effect, which significantly reduces the performance of semiconductor structures like DRAM.
Innovation Solution
A concave-convex surface is formed on the outer surface layer of active pillars, increasing the specific surface area of the gate oxide layer and enhancing gate control capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is continuously scaled down to optimize integration, then device integration density is improved, but gate control capability is weakened and short-channel effect becomes more obvious
Solution Approach 1:
The patent transforms the traditional planar gate structure into a three-dimensional wrapped gate structure that surrounds the active pillar. This dimensional change allows the gate to control the channel from multiple directions (top, bottom, and sidewalls), significantly enhancing gate control capability despite the continued scaling of transistor dimensions. The wrapped gate extends into the trench beneath the active pillar, providing additional control in the vertical dimension.
Solution Approach 2:
The patent employs curved and wrapped gate structures that conform to the cylindrical geometry of the active pillars. The gate oxide layer and conductive gate material are deposited to wrap around the curved sidewalls of the active pillars, maximizing the gate's control surface area and electrical field distribution. This curved geometry optimizes the electric field penetration into the channel region.
2Productivity
If transistor size is continuously scaled down, then device integration density is improved, but short-channel effect becomes more obvious, reducing semiconductor structure performance
Solution Approach 1:
The wrapped gate structure extends the gate's influence into the third dimension by wrapping around and extending into the trench beneath the active pillar. This provides enhanced control over the channel current from multiple angular directions, effectively suppressing short-channel effects that arise from reduced channel length in scaled devices.
Solution Approach 2:
The gate structure is nested within the trench that surrounds the active pillar, with the gate oxide layer forming an inner layer directly on the active pillar sidewalls and the conductive gate material forming an outer layer. This nested configuration maximizes the gate's control authority over the channel while maintaining compact device footprint.
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple active pillars arranged in an array on the substrate, where an outer surface layer of each of the active pillars has a concave-convex surface; forming a gate oxide layer on the substrate, where a filling region is formed between two adjacent active pillars in the same row; forming a word line and a first dielectric layer in the filling region; exposing a top surface of each of the active pillars; forming a contact layer on the top surface of each of the active pillars; and forming a capacitor structure on the contact layer.