Active Matrix Substrate Monolithic Gate Driver Area Reduction
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Solution Overview
Problem
Current active matrix substrates face challenges in reducing the circuit area and width of monolithic drivers, particularly due to the large size of output transistors and bootstrap capacitance portions, which also require transparent portions for sealing member inspection, further increasing circuit area.
Innovation Solution
The active matrix substrate incorporates a gate driver formed in a monolithic manner with a capacitance portion using transparent conductive layers, allowing for reduced circuit area by eliminating the need for transparent portions and optimizing the layout of capacitors, and includes an oxide semiconductor TFT with an In--Ga--Zn--O based semiconductor layer for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a monolithic gate driver is formed in the non-display region, then cost is reduced and mounting process is simplified, but the circuit area and width of the driver increase
Solution Approach 1:
The patent combines the gate driver circuit and capacitor into a single monolithic structure formed directly on the substrate. The capacitor is integrated within the driver circuit area, merging two previously separate components into one unified circuit block, thereby reducing overall circuit area while maintaining manufacturing simplicity
Solution Approach 2:
The patent implements nesting by placing the capacitor structure within or adjacent to the transistor structures of the gate driver. The capacitor occupies space that would otherwise be unused or partially used by the driver circuit, effectively nesting one component within the footprint of another to minimize total area
2Difficulty of detecting and measuring
If transparent portions are provided in the capacitor for sealing member inspection, then inspection is facilitated, but the capacitor area increases
Solution Approach 1:
The patent extracts the inspection function from the capacitor structure itself by providing dedicated inspection openings in the sealing member or substrate that allow optical access to the capacitor region. This separates the capacitor's electrical function from its inspection requirement, allowing the capacitor to maintain full area without transparent portions compromising its capacitance
Solution Approach 2:
The patent introduces an intermediary inspection structure (such as inspection openings in the sealing member or substrate) that mediates between the need for capacitor area and the need for inspection access. This intermediary allows optical inspection of the capacitor and surrounding structures without requiring the capacitor itself to have transparent portions
3Area of stationary object
If the output transistor and capacitor are disposed to overlap with the sealing member region, then circuit area is reduced, but inspection of the sealing member becomes difficult
Solution Approach 1:
The patent segments the inspection function from the circuit layout by providing dedicated inspection openings or access regions in the sealing member that are distinct from the circuit area. This allows the circuit to be disposed in the sealing member region for area reduction while maintaining separate, dedicated pathways for optical inspection of both the sealing member and capacitor
Data Source
AI summary
An active matrix substrate includes a peripheral circuit including a first TFT disposed in a non-display region and a capacitance portion, and a lower transparent electrode and an upper transparent electrode disposed in each pixel. The active matrix substrate includes a gate metal layer including a gate electrode of the first TFT, a source metal layer including a source electrode of the first TFT, a lower transparent conductive layer positioned above the gate metal layer and the source metal layer and including the lower transparent electrode, and an upper transparent conductive layer including the upper transparent electrode. The capacitance portion includes a first capacitor including a first lower capacitance electrode formed in the lower transparent conductive layer, a first upper capacitance electrode formed in the upper transparent conductive layer, and a portion positioned between these capacitance electrodes in a dielectric layer.