3D Memory Blocking Dielectric Layers With Dipole Tunneling Barriers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional memory devices face challenges in effectively managing electric dipole interfaces and charge tunneling, leading to inefficiencies in programming and erase operations due to unwanted charge tunneling and reduced data retention.
Innovation Solution
The implementation of a blocking dielectric film with specific layer configurations, including inner and outer silicon oxide layers and dielectric metal oxide layers, creates electric dipole interfaces that reduce electron tunneling and enhance programming efficiency by forming dipole moments, thereby improving data retention and erase saturation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional blocking dielectric layers are used in three-dimensional memory devices, then device structure is simpler, but unwanted charge tunneling occurs leading to reduced data retention and programming efficiency
Solution Approach 1:
The blocking dielectric layer is segmented into multiple distinct layers (first blocking dielectric layer, second blocking dielectric layer, and third blocking dielectric layer) with different compositions and functions. Each layer addresses specific aspects of charge tunneling control, with the first layer providing initial blocking, the second layer enhancing the barrier, and the third layer providing additional protection, collectively improving data retention without excessive complexity
Solution Approach 2:
The patent employs composite dielectric materials with different properties in each layer. The first blocking dielectric layer uses one material composition, the second layer uses a different composition optimized for dipole moment formation, and the third layer uses yet another composition for enhanced charge blocking. This composite structure allows optimization of each layer's properties to collectively solve the charge tunneling problem
2Productivity
If conventional single-layer blocking dielectric structures are used, then manufacturing process is simpler, but electron tunneling energy barrier is insufficient leading to reduced programming efficiency
Solution Approach 1:
The blocking dielectric function is segmented across three separate layers, each contributing to the overall electron tunneling barrier. The first layer provides baseline blocking, the second layer with its specific dipole-containing material creates an enhanced energy barrier through dipole moment formation, and the third layer provides additional blocking capability, collectively achieving superior programming efficiency
Solution Approach 2:
The patent changes multiple parameters across the layers including material composition, layer thickness, and dipole moment orientation. The second blocking dielectric layer specifically incorporates materials with controlled dipole moments to maximize the energy barrier height, while adjusting layer thicknesses to optimize the balance between blocking efficiency and manufacturing feasibility
3Quantity of substance
If thinner charge storage layers are used to increase density, then storage capacity improves, but charge tunneling control becomes more difficult reducing data retention
Solution Approach 1:
The three-layer blocking dielectric structure segments the charge blocking function to compensate for the reduced thickness of the charge storage layer. Each layer addresses different aspects of charge control, creating a distributed barrier system that maintains effective charge tunneling control even when the charge storage layer is thin, thereby preserving data retention while enabling higher density
Solution Approach 2:
The use of composite dielectric materials with different electrical properties in the three blocking layers creates a multi-faceted barrier against charge tunneling. The dipole-containing second layer specifically addresses the enhanced tunneling risk from thinner storage layers by creating an additional energy barrier, allowing thin charge storage layers to maintain reliable charge control
4Reliability
If conventional dielectric layers without dipole interfaces are used, then manufacturing is simpler, but energy barrier for electron tunneling is lower leading to unwanted charge tunneling
Solution Approach 1:
The dipole-containing second blocking dielectric layer is strategically positioned at the critical interface where charge tunneling is most problematic. This localized application of dipole materials concentrates the energy barrier enhancement exactly where needed, maximizing charge tunneling suppression while minimizing the complexity of incorporating dipole materials throughout the entire structure
Solution Approach 2:
The dipole-containing second blocking dielectric layer acts as an intermediary between the first and third blocking dielectric layers, creating an enhanced energy barrier through dipole moment formation. This intermediary layer mediates the charge blocking function, providing superior tunneling suppression that neither of the outer layers alone could achieve, while keeping the overall structure manufacturable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases energy barriers for electron tunneling, improves programming efficiency, and enhances data retention by suppressing unwanted charge tunneling and reducing threshold voltage distribution, while maintaining the advantages of thinner charge storage layers.
Implementation Method 1
The implementation of a blocking dielectric film with specific layer configurations, including inner and outer silicon oxide layers and dielectric metal oxide layers, creates electric dipole interfaces that reduce electron tunneling and enhance programming efficiency by forming dipole moments
Implementation Method 2
The memory film comprises a blocking dielectric film, a tunneling dielectric layer and a vertical stack of memory elements located between the blocking dielectric film and the tunneling dielectric layer
Data Source
AI summary
A memory device includes an alternating stack of insulating layers and electrically conductive layers arranged along a vertical direction, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film. The memory film includes a blocking dielectric film, a tunneling dielectric layer and a vertical stack of memory elements located between the blocking dielectric film and the tunneling dielectric layer. The blocking dielectric film includes component layers which include, from a side that is proximal to the vertical stack of memory elements toward a side that is distal from the vertical stack of memory elements, an inner silicon oxide blocking dielectric layer, a middle dielectric metal oxide blocking dielectric layer, an outer silicon oxide blocking dielectric layer, and an outer dielectric metal oxide blocking dielectric layer.