Stacked Folded Ferroelectric Bit-Cell Layout for Data Retention
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Solution Overview
Problem
Traditional non-volatile memories, such as ferroelectric memories, suffer from charge degradation and disturbance due to the routing configuration of plate-lines relative to bit-lines and word-lines, leading to polarization decay and leakage, which affects data retention and reliability.
Innovation Solution
The implementation of a stacked and folded capacitor configuration with word-line boosting and refresh mechanisms, including wear leveling schemes and error correction, to mitigate charge disturbance and enhance memory endurance, while also optimizing capacitor placement to reduce parasitic capacitance and improve data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional routing configuration of plate-lines relative to bit-lines and word-lines is used in ferroelectric memories, then device complexity is reduced, but charge disturbance and polarization decay occur leading to poor data retention
Solution Approach 1:
The patent transitions from planar capacitor layout to three-dimensional stacked capacitor configuration. Multiple capacitors are stacked vertically to share common electrodes, reducing the horizontal footprint while improving charge isolation. This vertical stacking arrangement minimizes parasitic capacitance and charge disturbance between adjacent memory cells, thereby enhancing data retention without significantly increasing overall device complexity.
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitors share common electrodes. The stacked capacitors are arranged such that inner capacitors share electrodes with outer capacitors, creating a compact nested configuration. This nesting approach reduces the total number of independent electrodes required, simplifies the overall device structure, and improves charge isolation between stored bits.
2Reliability
If multiple capacitors are used in memory bit-cells, then data retention is improved, but area occupied increases making them challenging for reduced dimensions
Solution Approach 1:
The patent employs vertical stacking of capacitors along the third dimension (z-axis) to accommodate multiple capacitors within a reduced planar footprint. By stacking capacitors vertically and sharing common bottom electrodes, the design achieves high storage density while minimizing the area occupied by each memory bit-cell, enabling scalability to reduced dimensions.
Solution Approach 2:
The patent merges multiple capacitors into a shared structure where adjacent capacitors share common electrodes. This combining approach reduces the total area required compared to completely independent capacitor structures, as shared electrodes eliminate redundant electrode areas and reduce the overall footprint of multi-capacitor memory bit-cells.
3Object-affected harmful factors
If stacked and folded capacitor configuration is implemented, then parasitic capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The stacked capacitor configuration utilizes vertical stacking with deliberate horizontal offsets between adjacent capacitors. This offset arrangement in three-dimensional space allows routing electrodes to pass through spaces between stacked capacitors, minimizing parasitic capacitance coupling while maintaining manufacturability through standard fabrication processes.
Solution Approach 2:
The patent segments the capacitor structure into distinct stacked units with clear separation between adjacent capacitors. This segmentation approach, combined with offset positioning, creates physical spacing that reduces parasitic capacitance while allowing independent optimization of each capacitor unit during manufacturing, thereby managing precision requirements.
Data Source
AI summary
A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.