Semiconductor Memory Device Refresh Sequence for Data Retention
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Solution Overview
Problem
Semiconductor memory devices with chalcogen-based variable resistance and nonlinear elements face challenges in maintaining optimal resistance states due to temperature-dependent resistance changes and voltage shifts, leading to potential data retention issues and increased bit error rates.
Innovation Solution
The semiconductor memory device employs a configuration with chalcogen layers as nonlinear elements, utilizing specific pulse operations (set, reset, and refresh sequences) and temperature management to maintain the resistance states, including a refresh sequence that increases the memory chip temperature to reduce resistance values and ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chalcogen-based variable resistance and nonlinear elements are used in memory cells, then high storage density and fast access speed are achieved, but temperature-dependent resistance changes and voltage shifts occur leading to data retention issues
Solution Approach 1:
The patent applies periodic refresh operations to memory cells storing data in high-resistance states. A refresh controller periodically detects voltage levels of memory cell word lines and applies refresh pulses to selected memory cells when voltage shifts indicate potential data loss. This periodic intervention prevents temperature-dependent drift from causing data retention failures while maintaining fast access speeds during normal operations.
Solution Approach 2:
The patent implements a feedback mechanism where the refresh controller continuously monitors voltage levels of memory cell word lines and adjusts refresh operations accordingly. When voltage shifts exceed thresholds indicating data retention risk, the controller activates refresh pulses; when voltage levels remain stable, refresh operations are reduced or suspended. This feedback-based approach dynamically maintains data reliability without unnecessary interference with normal memory operations.
2Reliability
If refresh operations are performed to maintain data integrity, then voltage shifts are corrected, but additional power consumption and operation time are required
Solution Approach 1:
The patent applies refresh operations selectively rather than universally to all memory cells. The refresh controller monitors voltage levels and applies refresh pulses only to memory cells exhibiting voltage shifts beyond acceptable thresholds. This partial action approach corrects data retention issues in affected cells while avoiding unnecessary power consumption from refreshing cells that maintain stable voltage levels, thereby balancing reliability with energy efficiency.
3Reliability
If the memory chip temperature is increased to reduce resistance values, then data retention is improved, but thermal management complexity and energy consumption increase
Solution Approach 1:
The patent utilizes temperature-dependent resistance characteristics of chalcogenide materials by dynamically adjusting operating parameters based on detected voltage levels. When voltage shifts indicate data retention risk, the system applies refresh pulses with amplitudes and durations designed to exploit thermal effects temporarily to restore proper resistance states. This parameter-based approach leverages inherent material properties without requiring sustained temperature increases, avoiding thermal management complexity while maintaining data reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively maintains the chalcogen layers in desired resistance states, preventing voltage shifts and data retention issues, thereby enhancing the reliability and longevity of the memory device.
Implementation Method 1
a variable resistance layer and a nonlinear element layer including chalcogen
Implementation Method 2
a refresh sequence that increases the memory chip temperature to reduce resistance values
Data Source
AI summary
A semiconductor memory device includes: first wirings; second wirings intersecting the first wirings; and memory cells. Each of the memory cells is respectively formed between one of the first wirings and one of the second wirings. In a set operation, a set pulse is supplied between one of the first wirings and one of the second wirings. In a reset operation, a reset pulse is supplied between one of the first wirings and one of the second wirings. In a first operation, a first pulse is supplied between one of the first wirings and one of the second wirings. the first pulse has an amplitude equal to or greater than the greater of an amplitude of the set pulse and an amplitude of the reset pulse and has a pulse width greater than a pulse width of the set pulse.