Semiconductor Spacer Patterning for Fine Pattern Yield
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Solution Overview
Problem
The existing methods for forming fine patterns in semiconductor devices face challenges due to resolution limits in lithography processes, leading to misalignment issues and reduced yield and reliability, especially in double exposure processes where the critical dimension of patterns is decreased, and the use of spacers to improve process margins results in dummy pattern degradation.
Innovation Solution
A method is developed where a spacer defines a fine pattern separate from the mask pattern, involving the formation of a sacrificial pattern, spacer formation, and subsequent etching to create a hard mask pattern, which improves the yield and reliability of semiconductor devices by preventing dummy pattern collapse and misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a double exposure process is used to form finer patterns, then the critical dimension is reduced and memory capacity is increased, but pattern misalignment occurs and manufacturing precision deteriorates
Solution Approach 1:
The patent segments the patterning process into multiple distinct steps: forming a first hard mask pattern, forming a sacrificial pattern, forming a spacer, and forming a second hard mask pattern. This segmentation allows each step to be optimized independently, achieving finer critical dimensions while maintaining alignment precision through the use of alignment marks and controlled deposition processes.
Solution Approach 2:
The patent employs preliminary actions by forming alignment marks and a sacrificial pattern before the final spacer formation. The sacrificial pattern is formed in advance with precise dimensions, and the spacer is subsequently formed on its sidewalls with controlled thickness. These preliminary structures serve as templates that ensure accurate final pattern alignment and critical dimension control.
2Reliability
If a spacer is formed on sidewalls of a sacrificial oxide pattern to improve process margin, then process margin is improved, but dummy pattern deteriorates and yield decreases
Solution Approach 1:
The patent applies local quality by treating the cell region and peripheral circuit region differently. In the cell region, a spacer is formed on the sidewalls of the sacrificial pattern to define fine patterns. In the peripheral circuit region, only a mask pattern is formed without a spacer, preserving the quality of dummy patterns. This localized approach allows process margin improvement where needed while maintaining dummy pattern integrity where required for yield.
3Quantity of substance
If the critical dimension is decreased to increase memory capacity in limited cell region, then memory capacity is increased, but resolution limit of exposer is exceeded and pattern formation becomes difficult
Solution Approach 1:
The patent uses a spacer as an intermediary structure to achieve fine patterns beyond the direct resolution capability of the exposer. The spacer is formed by depositing material on the sidewalls of a sacrificial pattern, and its thickness is controlled by deposition parameters rather than direct lithographic exposure. This intermediary approach allows critical dimensions smaller than the exposer's resolution limit to be achieved while maintaining manufacturing precision.
Data Source
AI summary
In a method for forming a fine pattern of a semiconductor device, forming a spacer for double patterning of a cell region is performed separate from forming a mask pattern that defines a dummy pattern for a pad of a peripheral circuit region.