3D FPGA Interconnect Architecture for High-Bandwidth Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Field-programmable gate arrays (FPGAs) and similar devices are limited by low interconnect density, leading to constraints on performance due to the cost and yield impact of adding layers, which restricts bandwidth and increases latency and power consumption.
Innovation Solution
A 3D semiconductor device architecture that combines an active die in an advanced node with a passive die in a legacy node, featuring dense interconnects and multiplexers, allowing for high bandwidth and reduced latency, with the passive die providing additional wiring without the need for expensive advanced node equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional layers are added to increase interconnect density in FPGAs, then routing capability and bandwidth are improved, but manufacturing cost and yield impact worsen due to expensive advanced node equipment
Solution Approach 1:
The device is divided into two separate layers: an active device layer fabricated in advanced node and a passive wiring layer fabricated in legacy node. This segmentation allows each layer to be optimized independently, with the passive layer providing additional interconnects without requiring expensive advanced node manufacturing equipment, thereby increasing interconnect density while controlling manufacturing costs
Solution Approach 2:
The patent transitions from a single-layer 2D architecture to a 3D stacked architecture by adding a passive wiring layer above the active device layer. This dimensional change enables additional routing paths and interconnects to be added vertically rather than horizontally, increasing interconnect density without proportionally increasing manufacturing complexity
2Quantity of substance
If embedded memory is used to handle all buffering for processing in FPGA, then memory bandwidth is improved, but latency and power consumption worsen
Solution Approach 1:
The patent adds a vertical dimension to the memory architecture by stacking the passive wiring layer above the embedded memory layer. This enables additional memory capacity and bandwidth through the stacked configuration, while the separation of active and passive functions allows for optimized power management, reducing overall power consumption despite increased memory capacity
3Adaptability or versatility
If more wiring layers are added to FPGAs to improve routing capability, then connectivity is improved, but device complexity and cost worsen
Solution Approach 1:
The routing functionality is segmented between the active device layer containing configurable elements and the passive wiring layer containing fixed interconnects. This segmentation allows the complex routing capability to be achieved by combining a simpler active layer with a dedicated passive wiring layer, improving routing capability while managing device complexity through functional separation
Solution Approach 2:
The passive wiring layer acts as an intermediary between the active device elements, providing additional routing paths and connectivity without requiring the active layer to become more complex. The passive layer mediates the interconnection needs, enabling enhanced routing capability while keeping the active device logic relatively simple
Data Source
AI summary
The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.