Compact RRAM Device With Conductive Sidewall Spacer
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Solution Overview
Problem
The scaling of flash memory devices is hindered by challenges such as program/erase voltages, access speed, and reliability, necessitating the development of more compact and efficient non-volatile memory solutions.
Innovation Solution
A compact RRAM device structure featuring a gate electrode, conductive sidewall spacer, and variable resistance material layers, with specific configurations and deposition processes to form unit cells on a semiconducting substrate, enabling efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If flash memory devices are scaled down to reduce size, then device footprint is reduced, but program/erase voltage control and reliability deteriorate
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage-based storage (flash memory) to resistance-based storage (RRAM). By utilizing variable resistance states in metal oxide layers instead of charge storage in floating gates, the device achieves reliable operation at scaled dimensions without suffering from voltage control degradation. The resistance switching mechanism remains effective regardless of device size reduction.
Solution Approach 2:
The patent replaces the charge-based electrical mechanism of flash memory with a resistance-based mechanism in RRAM. Instead of storing data as trapped charges in a floating gate that require precise voltage control, the invention uses variable resistance states in metal oxide materials that can be reliably switched and read at scaled dimensions, substituting one physical mechanism for another that is less sensitive to scaling effects.
2Productivity
If flash memory devices are scaled down, then integration density increases, but access speed deteriorates
Solution Approach 1:
The patent changes the speed-limiting parameter from charge tunneling time in flash memory to resistance switching time in RRAM. The resistance switching mechanism in metal oxide layers occurs on shorter timescales and is not constrained by the same quantum tunneling limitations that slow down scaled flash memory, enabling faster access speeds at higher integration densities.
3Measurement precision
If multiple pulses are applied to variable resistance material to produce incremental changes, then data storage precision improves, but energy consumption increases
Solution Approach 1:
The patent applies partial action by using multiple pulses of controlled amplitude and duration to achieve the desired resistance state change. Instead of applying one excessive high-energy pulse, the invention uses multiple lower-energy pulses that cumulatively achieve the same or better precision in setting the resistance state, thereby reducing overall energy consumption while maintaining or improving data storage precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The RRAM device achieves improved scalability, speed, and reliability by utilizing variable resistance materials, allowing for incremental changes in resistance without material damage, making it suitable for high-integration applications.
Implementation Method 1
The resistance of the variable resistance material layer may be varied or changed based upon the polarity and/or amplitude of an applied electric pulse. The electric field strength or electric current density from the pulse, or pulses, is sufficient to switch the physical state of the materials so as to modify the properties of the material.
Data Source
AI summary
Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer.