Segmented Drain Region Layout for Gate Dielectric ESD Protection
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Solution Overview
Problem
Integrated chips (ICs) are susceptible to damage from electrostatic discharge (ESD) pulses, particularly in open-drain buffer circuits, which can lead to catastrophic damage such as 'blowing out' gate dielectrics or 'melting' active regions, failing to meet ESD protection specifications for applications like HBM ESD class 2 and greater devices.
Innovation Solution
The IC design incorporates a drain region with two or more first doped regions and one or more second doped regions, where the first doped regions have a higher doping concentration and are spaced differently to create a high resistance across the drain region, reducing the voltage spike and preventing damage to the gate dielectric during ESD events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional drain region design is used, then the device structure is simple, but the ESD protection capability is insufficient and the gate dielectric can be damaged
Solution Approach 1:
The drain region is segmented into multiple first doped regions and second doped regions with different doping concentrations. This segmentation creates multiple resistance zones that work together to limit ESD current while maintaining normal device operation, thereby improving ESD protection without requiring a completely different device architecture.
Solution Approach 2:
Different regions within the drain are assigned different doping concentrations: first doped regions have higher concentration for normal operation, while second doped regions have lower concentration to create high resistance during ESD events. This local differentiation allows the same structure to serve dual purposes: normal switching and ESD protection.
2Reliability
If the doping concentration in the drain region is increased to reduce resistance, then normal device operation is improved, but ESD protection capability deteriorates due to higher current flow
Solution Approach 1:
The doping concentration parameter is varied spatially within the drain region. Second doped regions have lower doping concentration than first doped regions, creating a resistance gradient that limits ESD current flow. This parameter change allows the structure to present high resistance during ESD events while maintaining adequate conductivity for normal operation through the higher-doped first regions.
3Reliability
If additional doped regions are added to the drain, then ESD protection is improved, but manufacturing complexity increases
Solution Approach 1:
The drain region is divided into multiple doped regions (first and second doped regions) that can be formed using standard segmented doping techniques. This segmentation approach leverages existing manufacturing capabilities to create the complex doping profile without requiring entirely new process equipment or methods.
Solution Approach 2:
Different doping concentrations are applied to different spatial regions within the drain. This local quality differentiation can be achieved through selective masking and doping processes that are extensions of conventional semiconductor manufacturing, allowing the complex structure to be fabricated using adapted standard processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances ESD protection, allowing the IC to withstand ESD pulses with voltages greater than or equal to 2,000 V, meeting or exceeding specifications for HBM ESD class 2 and greater devices.
Implementation Method 1
the first doped regions have a higher doping concentration and are spaced differently to create a high resistance across the drain region, reducing the voltage spike
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.