Split-Gate Nonvolatile Memory Cell Mask Reduction
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Solution Overview
Problem
The existing semiconductor manufacturing processes for nonvolatile memory devices require multiple masks and complex alignment steps, making it difficult to achieve high-density integration and efficient charge retention, particularly due to issues with the floating gate method's miniaturization and the MONOS method's poor charge retention.
Innovation Solution
A simplified manufacturing process that reduces the number of masks by using a split-gate structure with a MONOS memory cell, where a dedicated contact region is formed using self-alignment techniques, allowing for high-speed operation and improved charge retention without electrical shorts, and enabling denser integration by eliminating the need for additional siliciding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the floating gate method is used for charge storage, then charge retention characteristics are good, but device miniaturization is limited due to the requirement of at least 8 nanometers thick oxidized film
Solution Approach 1:
The patent changes the charge storage mechanism from floating gate to MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure, altering the physical parameters of charge retention. The MONOS structure uses a nitride layer to trap charges, enabling thinner oxidized films (less than 8 nanometers) while maintaining adequate charge retention, thus resolving the contradiction between reliability and device size.
2Manufacturing precision
If multiple masks are used for forming contact regions and gate electrodes, then alignment precision can be maintained, but manufacturing complexity and process time increase
Solution Approach 1:
The patent merges the formation of contact regions and gate electrodes into a single lithography step using a unified mask pattern. The mask simultaneously defines both the contact region boundaries and the gate electrode positions, eliminating the need for separate alignment steps and reducing manufacturing complexity while maintaining precision through the self-aligned nature of the split-gate structure.
Solution Approach 2:
The contact region is formed preliminarily as part of the gate electrode pattern definition. By pre-defining the contact region boundaries within the same mask pattern used for gate electrodes, the patent ensures proper alignment is achieved before actual electrode formation, simplifying the overall manufacturing process.
3Reliability
If additional siliciding processes are added to prevent electrical shorts, then reliability improves, but manufacturing time and process complexity increase
Solution Approach 1:
The patent employs a self-aligned split-gate structure where the gate electrode automatically serves as a barrier preventing electrical shorts between contact regions. The physical separation created by the gate electrode itself eliminates the need for additional siliciding protection processes, as the structure inherently prevents short circuits while maintaining manufacturing efficiency.
Data Source
AI summary
Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed adjoining the selected gate electrodes. A contact is set on a wiring layer self-aligned by filling side-wall gates of polysilicon in the gap between the electrodes and auxiliary pattern. The contact may overlap onto the auxiliary pattern and device isolation region, in an optimal design considering the size of the occupied surface area. If the distance to the selected gate electrode is x, the ONO film deposit thickness is t, and the polysilicon film deposit thickness is d, then the auxiliary pattern may be separated just by a distance x such that x<2×(t+d).