Semiconductor Device Integrating Memory Structure with Transistor
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Solution Overview
Problem
The BEOL process for forming memory cells in semiconductor devices is complex, results in low manufacturing yield, and limits memory cell density, necessitating design modifications for process simplification and density enhancement.
Innovation Solution
A semiconductor device and manufacturing method that integrate a memory structure with a transistor structure, featuring a substrate, semiconductor channel layer, gate electrode, and a first memory structure with a bottom plate, top plate, and memory element layer, where the bottom plate contacts the semiconductor channel layer, simplifying the process and enhancing memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are formed by the BEOL process, then the integrity of the integrated circuit is improved, but the process complexity increases and manufacturing yield decreases
Solution Approach 1:
The patent merges the memory cell formation process with the transistor formation process by integrating the capacitor structure into the same fabrication sequence. The bottom plate of the capacitor is formed simultaneously with the source/drain regions of the transistor, and the dielectric layer is deposited over both structures together, thereby reducing process complexity while maintaining integrated circuit integrity
2Reliability
If memory cells are formed by the BEOL process, then the integrity of the integrated circuit is improved, but the manufacturing yield decreases
Solution Approach 1:
The patent combines memory cell and transistor fabrication into a single integrated process flow, where both structures are formed simultaneously using the same deposition and patterning steps. This merging reduces the total number of process steps and minimizes variability between separate fabrication sequences, thereby improving manufacturing yield while maintaining circuit integrity
3Reliability
If memory cells are formed by the BEOL process, then the integrity of the integrated circuit is improved, but the memory cell density is limited
Solution Approach 1:
The patent utilizes vertical stacking to increase memory cell density. The capacitor structure is built in the vertical dimension with multiple layers including the bottom plate, dielectric layer, and top plate extending upward from the substrate. This three-dimensional arrangement allows more memory cells to be packed into the same planar area while maintaining the integrity of the integrated circuit through controlled vertical integration
Data Source
AI summary
A semiconductor device includes a substrate, a semiconductor channel layer, a gate electrode, and a first memory structure. The semiconductor channel layer is disposed on the substrate. The gate electrode and the first memory structure are disposed on the semiconductor channel layer. The first memory structure includes a first bottom plate, a first top plate, and a first memory element layer. The first top plate is disposed on the first bottom plate. The first memory element layer is disposed between the first bottom plate and the first top plate. The first bottom plate contacts the semiconductor channel layer. Purposes of process simplification and/or memory density enhancement may be achieved by integrating a transistor with a memory structure.