Flash Memory Logical Cell Mapping for Byte Alterability
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Solution Overview
Problem
Conventional flash memory devices cannot be rewritten to the same address location without erasing an entire sector or block, limiting their ability to support byte alterability and requiring sector-level erasure, which is a time-consuming process.
Innovation Solution
The innovation involves mapping two adjacent physical memory cells as a single logical cell, creating a single program and erase entity that allows for logical cell erase, program, and read operations on a byte or variable bit length basis, enabling byte alterability by combining neighboring drain/source regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional flash memory devices are used with sector-level erasure, then data storage capacity is maintained, but write speed and operational efficiency deteriorate due to the requirement of erasing entire sectors before rewriting
Solution Approach 1:
The patent segments the flash memory structure by mapping two adjacent physical memory cells to form a single logical memory cell. This segmentation allows independent programming and erasing of individual logical cells without requiring erasure of entire sectors, thereby improving write speed and operational efficiency while maintaining data storage capacity
Solution Approach 2:
The patent introduces a new dimension of logical cell mapping that overlays the physical cell structure. By creating logical cells that span multiple physical cells, the system enables byte alterability and single-bit programming operations, transforming the conventional sector-level operation model into a more granular, efficient operation model
2Reliability
If sector-level erasure is performed in conventional flash devices, then data integrity is maintained, but time consumption increases due to the large erasure unit size
Solution Approach 1:
By dividing the memory into logical cells that are smaller than physical sectors, the patent enables selective erasure of only the necessary data units. This segmentation maintains data integrity through controlled erasure while significantly reducing the time required compared to erasing entire sectors
Solution Approach 2:
The patent performs preliminary mapping of physical cells to logical cells, establishing a structure that enables direct access and selective operation on individual logical cells. This preliminary organization allows subsequent erasure and programming operations to be performed efficiently on only the required data units
3Adaptability or versatility
If byte alterability is implemented in flash devices, then operational flexibility improves, but device complexity increases due to the need for additional mapping and control mechanisms
Solution Approach 1:
The patent implements byte alterability by segmenting physical cells into logical cells with a mapping structure. This segmentation provides operational flexibility for single-bit and byte-level programming while managing complexity through a systematic mapping approach that can be implemented in existing flash memory architectures
Solution Approach 2:
The logical cell mapping structure serves multiple functions: it enables byte alterability, supports single-bit programming, allows selective erasure, and maintains compatibility with existing flash memory interfaces. This multi-functionality achieves operational flexibility without proportionally increasing device complexity
Data Source
AI summary
Flash memory systems and methodologies are provided herein for providing byte alterability in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a logical cell for emulating byte alterability. By mapping two adjacent physical cells as a single logical cell, the logical cell is a combination of neighboring drain/source regions, thereby creating a single program and erase entity. The single program and erase entities can allow for logical cell erase and program in either direction of a low voltage state or a high voltage state on a single bit or variable bit length basis. By employing the single program and erase entity, the subject innovation can provide a cost-effective approach to emulating electrically EEPROM in a flash device.