Surfactant-Free Cleaning for Semiconductor Gate Lines
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Solution Overview
Problem
The increasing integration density of semiconductor memory devices leads to interference between memory cells, and existing cleaning methods, particularly wet methods using buffered oxide etchant (BOE) solutions, fail to completely remove residues, causing defects and damaging gate lines due to high viscosity, acidity, and surfactant-induced permeation into air gaps.
Innovation Solution
A surfactant-free cleaning solution with viscosity lower than 2 cP and acidity lower than 3 pH is used to remove residues from the surface of the insulating layer, preventing damage to gate lines and maintaining air gaps by using a hydrofluoric acid (HF) solution or standard clean (SC)-1 solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a wet cleaning process using BOE solution is performed to remove residues, then cleaning effectiveness is improved, but the cleaning solution flows into exposed air gaps causing defects
Solution Approach 1:
The patent changes the physical parameters of the cleaning solution by adjusting temperature and viscosity. The cleaning solution is maintained at a temperature of 40°C to 60°C, which reduces its viscosity and prevents it from flowing into air gaps while maintaining effective residue removal capability.
Solution Approach 2:
The patent applies a protective coating on the insulating layer before the wet cleaning process. This protective layer acts as a barrier that prevents the cleaning solution from penetrating into exposed air gaps, thereby cushioning against potential defects while allowing effective residue removal.
2Manufacturing precision
If BOE solution with high acidity is used for cleaning, then residue removal capability is improved, but gate lines are oxidized and damaged
Solution Approach 1:
The patent changes the chemical parameters of the cleaning solution by adjusting pH and replacing BOE with alternative cleaners. The cleaning solution is formulated with pH controlled at 8.0 to 10.0, and uses alternatives like ammonium hydroxide-based solutions or surfactant-containing cleaners that provide effective residue removal without the strong oxidizing action of high-acidity BOE solutions, thus preventing gate line damage.
3Manufacturing precision
If surfactant-containing cleaning solution is used, then cleaning effectiveness is improved, but the solution permeates deeply into air gaps and remains after drying
Solution Approach 1:
The patent changes the physical parameters of the cleaning solution by controlling viscosity through temperature adjustment. By maintaining the cleaning solution at 40°C to 60°C, the viscosity is reduced, allowing the solution to be easily removed after cleaning without deep permeation into air gaps, while still maintaining effective residue removal capability.
Solution Approach 2:
The patent employs a multi-step cleaning process with periodic actions: initial wet cleaning, followed by rinsing, and then drying. This periodic action ensures that the cleaning solution is systematically removed from the surface and air gaps, preventing retention that would cause defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively inhibits oxidation and collapse of gate lines, increases yield, and improves the reliability of semiconductor memory devices by preventing the cleaning solution from flowing into air gaps and ensuring uniform patterns.
Implementation Method 1
the cleaning process is typically performed using a wet method
Implementation Method 2
the gate lines 12 may be partially oxidized due to hydroxide (OH−) ions or bifluoride (HF2−) ions from the BOE solution
Implementation Method 3
a cleaning solution may flow into the exposed air gaps
Data Source
AI summary
A method of manufacturing a semiconductor memory device comprises forming a plurality of gate lines on a semiconductor substrate, forming an insulating layer on the gate lines, and performing a cleaning process using a surfactant-free cleaning solution having a viscosity of lower than 2 cP and an acidity of lower than 3 pH to remove residue from the surface of the insulating layer.