Array Substrate Diagonal Transistor Layout for Short Circuit Maintenance
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Solution Overview
Problem
The dual-gate array substrate design increases the likelihood of short circuits between adjacent gate lines or gate electrodes, making defect maintenance complex and time-consuming, especially when the short circuit occurs in the crossed region of data and gate lines, requiring the removal and reconnection of gate lines to prevent data line cutoff.
Innovation Solution
The array substrate configuration includes first and second gate lines positioned on either side of pixel units, with transistors diagonally disposed and connected to both gate lines, allowing for selective cutting off of short circuits at specific connection points away from the data line, preventing data line cutoff and enabling efficient maintenance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dual-gate design is used to improve voltage linearity and image quality, then image quality is improved, but the likelihood of short circuits between adjacent gate lines or gate electrodes increases
Solution Approach 1:
The patent applies asymmetry by positioning transistors diagonally rather than symmetrically, and by placing gate lines at upper and lower sides of pixel rows rather than symmetrically around them. This asymmetric arrangement increases the distance between adjacent gate lines and gate electrodes, reducing short circuit risk while maintaining the dual-gate voltage linearity benefits
Solution Approach 2:
The patent transitions from a planar arrangement to a three-dimensional spatial arrangement by positioning gate lines at upper and lower sides of pixel rows and transistors diagonally adjacent to data lines. This dimensional change creates additional spacing between conductive elements, reducing short circuit probability while preserving dual-gate functionality
2Reliability
If cutting is performed to resolve short circuit between gate lines or gate electrodes in crossed region, then short circuit is resolved, but data line is cut off together requiring complex maintenance
Solution Approach 1:
The patent segments the gate line connections by providing separate connection points for first and second gate lines to their respective gate electrodes. This segmentation allows independent cutting and maintenance of gate line connections without affecting data lines, as each gate line can be addressed separately at its dedicated connection point
Solution Approach 2:
The patent introduces separate connection points as intermediary elements between gate lines and gate electrodes. These intermediaries allow for selective cutting and maintenance of gate connections without involving data lines, simplifying the maintenance process by providing dedicated access points for gate line repairs
3Reliability
If gate line is removed and reconnected to maintain short circuit, then short circuit is fixed, but maintenance time increases and work efficiency decreases
Solution Approach 1:
The patent performs preliminary action by establishing separate connection points for gate lines during the manufacturing process. This preliminary setup enables rapid maintenance operations, as technicians can directly cut and reconnect gate lines at pre-positioned connection points without requiring complex removal and reconnection procedures, significantly reducing maintenance time
Data Source
AI summary
An array substrate includes a pixel unit, a data line, a first gate line and a second gate line. Adjacent two columns of pixel units are collectively connected to one data line, adjacent two of the pixel units in each row of pixel units are respectively connected to the first and second gate lines, the pixel unit includes a transistor, and the transistor in each pixel unit is provided adjacent to the data line. In adjacent two columns of pixel units, transistors of two diagonally adjacent pixel units are provided adjacent to the data line and connected respectively to the first and second gate lines. The first and second gate lines surround the gate electrode of the transistor, respectively, and the first and second gate lines are connected to the gate electrode of the transistor at positions of the gate electrode away from the data line.