U-Shaped Channel Memory Device for High-Density NAND Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As critical dimensions in integrated circuits shrink, there is a need for techniques to enhance storage capacity and reduce costs per bit in NAND memory devices, while existing technologies face challenges in achieving these goals effectively.
Innovation Solution
A memory device design featuring a U-shaped channel element with a gate electrode layer and memory elements surrounding its sidewall surface, comprising multiple memory layers with varying compositions and arrangements to optimize storage capacity and electrical coupling, allowing for efficient NAND memory string formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If critical dimensions are shrunk to increase storage capacity, then storage capacity is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional vertical and U-shaped channel structures. This dimensional change allows storage capacity to increase by utilizing vertical space and multiple sidewalls, while the self-aligned fabrication process maintains manufacturing precision despite the increased complexity of the three-dimensional structures.
Solution Approach 2:
The patent implements nested structures where memory elements are formed around the sidewalls of channel structures, and multiple layers are stacked vertically. This nesting approach increases storage capacity by utilizing the three-dimensional space efficiently, while the self-aligned process ensures that each nested layer is precisely positioned relative to the others.
2Quantity of substance
If memory layers are increased to enhance storage capacity, then storage capacity is improved, but device complexity worsens
Solution Approach 1:
The patent divides the memory device into multiple functional layers (tunnel insulation layer, charge trapping layer, blocking insulation layer) stacked vertically around the channel sidewalls. This segmentation allows each layer to perform a specific function, increasing storage capacity through multiple memory layers while the self-aligned fabrication process manages the complexity by automatically positioning each segment correctly.
Solution Approach 2:
The gate electrode structure serves multiple functions: it controls the channel, provides electrical connections, and acts as a reference for aligning memory layers during fabrication. This multi-functionality reduces device complexity by combining several roles into a single structure, while still supporting increased storage capacity through multiple memory layers.
3Quantity of substance
If U-shaped channel structures are formed to improve storage capacity, then storage capacity is improved, but ease of manufacture worsens
Solution Approach 1:
The patent uses sacrificial structures that are formed first, then memory layers are deposited around them in a self-aligned manner, and finally the sacrificial structures are removed. This preliminary action sequence simplifies manufacturing by using the sacrificial structures as temporary guides that automatically define the final U-shaped channel geometry, eliminating the need for complex direct patterning of the U-shape.
Solution Approach 2:
The sacrificial structures act as intermediaries during fabrication. They are temporarily present to guide the formation of memory layers around the channel, then removed after serving their purpose. This intermediary approach simplifies manufacturing by providing a temporary reference framework that makes the complex U-shaped structure formation process more manageable.
Data Source
AI summary
A memory device includes a channel element, a gate electrode layer and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds a sidewall channel surface of the channel element.