3D Memory Structure With Charge Trapping Multilayers
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Solution Overview
Problem
Current 3D stacked memory structures with double gate or surrounding gate unit cells face challenges in size reduction and manufacturing complexity, while maintaining charge retention and electrical performance, which limits their potential for greater storage capacity and cost-effectiveness.
Innovation Solution
A 3D memory structure with single gate unit cells, featuring a bottom gate connected to multiple stacked structures, charge trapping multilayers, ultra-thin channels, and independently controlled selection lines, along with a dielectric layer and word line selectors, which simplifies the design and reduces disturbance between word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If double gate or surrounding gate unit cells are used, then charge retention is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the gate function from the charge trapping multilayer structure, placing the gate electrode separately above the charge trapping layer rather than integrating it within the multilayer. This separation simplifies the unit cell structure while maintaining effective charge control and retention capabilities through the dedicated gate electrode configuration.
Solution Approach 2:
The patent segments the memory structure into distinct functional layers: charge trapping multilayer, gate electrode, and tunnel insulator layer. This segmentation allows each component to be optimized independently, reducing manufacturing complexity while preserving charge retention performance through specialized material and structural design in each layer.
2Reliability
If charge trapping multilayer thickness is increased, then charge retention is improved, but unit cell size reduction capability is limited
Solution Approach 1:
The patent transitions from planar charge storage to three-dimensional charge trapping by forming vertical charge trapping multilayers and ultra-thin channels. This dimensional change allows sufficient charge retention capacity without increasing lateral unit cell dimensions, as charge is trapped in the vertical thickness direction rather than requiring larger planar area.
Solution Approach 2:
The patent employs ultra-thin channel structures with thicknesses of 5 nm or less, creating flexible, conformal charge trapping regions that can maintain adequate charge retention capacity in reduced thickness while enabling significant lateral size reduction of unit cells through the thin-film vertical channel architecture.
3Reliability
If more spaces are occupied by charge trapping multilayer, then charge retention is improved, but design rules for size reduction become more complex
Solution Approach 1:
The patent segments the charge trapping function into a dedicated multilayer structure separate from the gate control, allowing independent optimization of charge retention (through multilayer composition and thickness) and device size (through gate and channel dimensions). This segmentation simplifies design rules by decoupling the two competing requirements.
Solution Approach 2:
The patent applies different material compositions and structural properties to different regions: the charge trapping multilayer uses specific dielectric materials optimized for charge storage, while the ultra-thin channels use semiconductor materials optimized for carrier transport. This local quality differentiation allows each region to be optimized for its specific function without compromising overall device performance or increasing design complexity.
4Length of moving object
If single gate unit cells are used, then size reduction capability is improved, but word line disturbance increases
Solution Approach 1:
The patent introduces a gate electrode as an intermediary between the control gate and the charge trapping multilayer. This intermediary structure allows the control gate to influence the channel without direct contact with the charge trapping region, reducing capacitive coupling and word line disturbance while maintaining effective charge control through the gate electrode.
Solution Approach 2:
The patent reduces word line disturbance by transitioning to vertical field effect through the ultra-thin channel structure. The electric field from the control gate acts vertically through the thin channel to modulate charge trapping, rather than relying on lateral field extension that causes disturbance to adjacent word lines. This vertical field confinement minimizes cross-talk between stacked memory layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables greater storage capacity, improved electrical properties, and reduced manufacturing costs by allowing for smaller unit cells with enhanced charge retention and stability, while minimizing the complexity of the manufacturing process.
Implementation Method 1
a plurality of charge trapping multilayers formed outsides of the stacked structures and extending to the bottom gates
Implementation Method 2
the gate insulator fills between the selection lines, between the gate and the selection lines and forms on top of the selection lines for insulation
Data Source
AI summary
A three-dimensional memory structure is provided, comprising plural stacked structures vertically formed on a substrate, each stacked structure comprising a bottom gate, wherein the bottom gates of the stacked structures are electrically connected; plural gates and gate insulators alternately stacked on the bottom gate; and two selection lines formed above the gates and spaced apart form each other and the selection lines being independently controlled, wherein the gate insulator fills between the selection lines, between the gate and the selection lines and forms on top of the selection lines for insulation. The 3D memory structure further comprises plural charge trapping multilayers formed outsides of the stacked structures and extending to the bottom gates; plural ultra-thin channels formed outsides of the charge trapping multilayers and lined between the adjacent stacked structures; and a dielectric layer formed between the ultra-thin channels and between the stacked structures.