3D Memory Chip Bonded to Both Sides of Support Die
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Solution Overview
Problem
Three-dimensional memory devices face limitations due to degradation of peripheral circuitry from thermal cycling and hydrogen diffusion, and the number of word lines in these devices is constrained by etch processes, limiting the vertical stacking capacity.
Innovation Solution
A three-dimensional memory chip design where memory dies are bonded to both sides of a support die, with CMOS devices on the support die providing peripheral circuitry, and memory elements are stacked vertically to enhance performance and increase word line capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory dies are bonded to both sides of a support die, then vertical stacking capacity and word line capacity increase, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from traditional planar memory architecture to a three-dimensional stacked architecture by bonding memory dies to both front and back sides of a support die. This vertical stacking approach multiplies the number of word lines by utilizing the third dimension (height), thereby increasing storage capacity without expanding the footprint area.
Solution Approach 2:
The memory system is divided into multiple independent memory dies that can be manufactured separately and then bonded to the support die. Each memory die functions as an independent unit, allowing for modular manufacturing, testing, and assembly, which manages the complexity of the overall system.
2Adaptability or versatility
If peripheral circuitry is integrated on the same substrate as memory devices, then device integration is improved, but peripheral circuitry degrades due to thermal cycling and hydrogen diffusion
Solution Approach 1:
The patent separates the memory array functionality (in memory dies) from the peripheral circuitry functionality (in the support die). This physical segmentation allows each component to be optimized independently: memory dies can be designed for high-density storage while the support die houses CMOS peripheral circuitry that requires stable thermal and chemical environments.
Solution Approach 2:
The support die acts as an intermediary platform that provides peripheral circuitry services to multiple memory dies without being directly exposed to the harsh conditions (thermal cycling, hydrogen diffusion) that occur during memory device operation. This mediator approach protects the sensitive CMOS circuitry while enabling integration.
Data Source
AI summary
A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.