3D Non-Volatile Memory Device CMP Dummy Area Reduction
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Solution Overview
Problem
Conventional semiconductor storage devices face challenges in reducing the area occupied by memory layers and CMP dummy layers, limiting further refinement and increasing costs due to the need for expensive EUV exposure devices and physical limitations such as breakdown voltage.
Innovation Solution
A non-volatile semiconductor storage device design featuring a configuration with stepwise ends of conductive layers and a method of manufacturing that includes forming through holes and insulation layers to reduce the area occupied by the CMP dummy layers, allowing for more efficient integration and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a three-dimensional manner with multiple laminated conductive layers and CMP dummy layers, then memory storage capacity is improved, but the area occupied by the device increases
Solution Approach 1:
The patent applies dimensionality change by arranging memory cells in a three-dimensional configuration with multiple laminated conductive layers (first through fourth conductive layers) stacked perpendicular to the substrate. This vertical stacking enables increased memory storage capacity without proportionally increasing the planar device area, as multiple memory strings are formed within the same footprint by utilizing the vertical dimension for layer stacking.
Solution Approach 2:
The patent implements multi-functionality by designing the second conductive layer to serve dual purposes: it functions as both a control gate for memory cells in the second region and as a CMP dummy layer in the third region. This eliminates the need for separate CMP dummy layers, reducing the overall device area while maintaining the necessary planarization function during manufacturing.
2Length of moving object
If further refinement is achieved through conventional photolithography, then device dimension is reduced, but manufacturing cost increases due to EUV exposure requirements
Solution Approach 1:
The patent applies segmentation by dividing the substrate into multiple distinct regions (first, second, and third regions) with different functional configurations. This segmentation allows each region to be optimized independently, enabling further refinement of device dimensions through targeted processing in specific areas without requiring expensive EUV exposure across the entire wafer, thus reducing manufacturing costs.
3Manufacturing precision
If memory layers and CMP dummy layers are both provided on the substrate, then manufacturing precision is improved, but the area occupied by these layers increases
Solution Approach 1:
The patent implements multi-functionality by designing the second conductive layer to serve dual purposes: it functions as both a control gate for memory cells in the second region and as a CMP dummy layer in the third region. This eliminates the need for separate CMP dummy layers, reducing the overall device area while maintaining the necessary planarization function during manufacturing.
Data Source
AI summary
A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction. The second layer includes: a plurality of second conductive layers extending in parallel to the substrate and laminated in a direction perpendicular to the substrate, the second conductive layers being formed in the same layer as the plurality of first conductive layers; and a second insulation layer formed on an upper layer of the plurality of second conductive layers. Respective ends of the second conductive layers are formed to align along a straight line extending in a direction substantially perpendicular to the substrate at a predetermined area.