Solid-State Devices TRIZ Cases

Low-temperature compression embeds wet-etched solder pads into connection bumps, resolving weak bonding strength and reliability issues.

Organic insulating dams prevent edge tail formation and seal the device against oxygen penetration.

A segmented mirror pattern defines transmission windows in an OLED display to route light to a camera sensor.

A light emitting device uses a patterned second ohmic layer to form extraction structures without damaging the underlying first conductive layer.

A fabricating method forms a metal silicide pattern in an etch stop layer to expand the contact area between a storage node plug and electrode.

Trench MOSFET diode clamps high voltage between gate and source metals, reducing on-state resistance by omitting the traditional resistor.

Patterned cap bonding with compatible adhesive protects signal conditioning circuitry while exposing sensing elements to ambient conditions.

Capacitive pressure sensor minimizes parasitic capacitance noise by segmenting electrodes into separate layers, enabling accurate micro-pressure detection.

Removing the rigid glass substrate enables a lightweight, shock-resistant flexible radiation detector.

Integrating SIMM and DIMM contacts into one connector reduces manufacturing complexity while supporting distinct signal transmission configurations.

A modular data transfer architecture uses port mappers to route global addresses across interconnected tiles within a system on chip.

Corrugated semiconductor substrates create segmented channel regions in MOSFETs to suppress source-to-drain leakage currents while maintaining carrier mobility.

Integrated buffer and doping layers in stacked OLED sub-devices reduce band gaps to enhance electron injection efficiency and extend device lifetime.

Graded III-V compound drain regions improve conductivity and reliability while managing manufacturing complexity in 3D memory structures.

Bank layer offsets column arrays and inkjet nozzles switch groups to prevent continuous erroneous ejection that causes stripe unevenness.

Metal gate electrodes lower resistance to boost operation speed while preventing process defects during fabrication.

Overlapping color filters on an array substrate create a smooth surface template for liquid crystal material application.

Electrochemical etching creates porous silicon templates that enable selective epitaxial growth, resolving reliability constraints in SOI positioning.

Segmented blue phase layers with multi-directional electric fields improve white transmittance and contrast ratio.

A tapered light-blocking wall at pixel boundaries reflects incident light directly onto photoelectric conversion units.

Integrating a transparent conductive material into the common electrode reduces capacitive coupling interference and increases the aperture ratio.

Groove-filling sealant traps dicing debris on sidewalls, preventing contamination of CMOS image sensor pixels and boosting fabrication yield.

Vertical trenches in cadmium zinc telluride detectors lengthen the conductive path between electrodes, reducing electron leakage without increasing pixel area.

Segmented emissive layers with varying emitter concentrations confine excitons to reduce quenching and improve OLED efficiency.

Peripheral protrusions on light-emitting layers contact bank side surfaces to prevent excess current flow and maintain luminance consistency across sub-pixels.

A magnetic memory device sets electric potentials on a first magnetic layer to control magnetization orientation for stable programming.

Annealing a conductive layer on a gate insulating film flows material into voids, eliminating gaps that reduce contact reliability.

Precise silicon oxynitride composition balances durability and luminous efficiency in display panels.

Segmenting epitaxial growth from the final device structure eliminates handling complexity while enabling precise color point control for white light emission.

Vertical recess structures extend control gates beneath floating gates to boost coupling ratios without increasing lateral device footprint.

A solar cell system uses an arc-shaped surface to expose the P-N junction directly to incident light beams.

A wafer processing method uses laser-induced strength reduction and radial tape tension to separate device chips along division lines.

Direct electrical connections through gate insulation layer vias eliminate transparent electrodes, reducing peripheral circuit area for narrower display frames.

Iterative pre-simulation and post-simulation adjust microlens de-centering values to correct non-symmetric brightness distribution across the sensor die.

Matching resistance and capacitance in reference cells reduces current variations, increasing read margins for faster non-volatile memory access.

Alloy gate and source drain electrodes reduce IR Drop to improve brightness uniformity while maintaining bending resistance.

Uniform slits on DBS common electrode wires mitigate horn-shaped terrain at color-resist overlaps, reducing light leakage and improving contrast.

Uniformly distributed insulating impurities modify phase change layer properties to lower reset current requirements.

Replacing preserving layers with L11 alloys and textured dielectrics reduces device thickness while maintaining thermal stability.

Annular mask openings trap migrating raw material to prevent oversized nano-columns and maintain light emission efficiency.

A brightness enhancement film and lambda/2 phase-difference plate arranged between a lambda/4 plate and linear polarization plate in an OLED optical member.

Segmented housing bodies linked by a multi-functional leadframe resolve the trade-off between mounting flexibility and structural complexity.

Specific adhesive thickness ratios between display panel and touch module absorb folding stress to prevent electrode cracks during bending.

A magnetoresistance effect element uses a channel layer and recording layer to store neural network weights via current pulses.

A wafer processing method using cut grooves and laser irradiation to divide chips while applying a liquid die bonding agent on the back surface.

Intermediary conductive wiring layers draw leakage current from a common hole injection layer, suppressing color mixture and improving image quality.

A display substrate design exposes the semiconductor layer through the color filter to reduce parasitic capacitance between gate and source electrodes.

A dual-pulse method accumulates charges in a PIN diode rectifying element via impact ionization, boosting on-current while suppressing off-current leakage.

Selective photopolymerization forms a compliant interface layer that facilitates reliable adhesive attachment of miniaturized LEDs during display manufacturing.

A pixel structure uses a reflective pixel electrode covering bumps to enhance reflectivity in transmissive and reflective modes.