MOSFETs on Corrugated Substrates for Leakage Control
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Solution Overview
Problem
Conventional MOSFET designs face challenges in scaling down to improve cost and performance, as techniques to reduce static power consumption, such as increasing channel doping and decreasing gate-dielectric thickness, often lead to decreased transistor performance and variability due to increased source-to-drain leakage currents and degraded carrier mobility.
Innovation Solution
The formation of MOSFETs using a semiconductor substrate with precisely-formed and regularly-spaced stripes (ridges) that create segmented channel regions, allowing for enhanced control over source-to-drain leakage currents and improved performance consistency, achieved through the use of heavily doped sub-surface regions and wrapped gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If channel doping concentration is increased to reduce source-to-drain leakage current, then static power consumption is reduced, but carrier mobility is degraded and on-current decreases
Solution Approach 1:
The channel region is segmented into multiple sections with different doping concentrations. The first channel section has higher doping to suppress leakage, while the second channel section has lower doping to maintain carrier mobility and on-current. This segmentation allows simultaneous optimization of both static power consumption and transistor performance.
2Loss of energy
If gate dielectric thickness is decreased to increase gate capacitance and control channel potential, then source-to-drain leakage is suppressed, but gate-to-channel leakage increases
Solution Approach 1:
The gate dielectric structure is optimized locally with a first gate dielectric layer having different properties than a second gate dielectric layer. This local quality variation allows the gate to exert sufficient control over the channel to suppress source-to-drain leakage while maintaining adequate breakdown strength to prevent gate-to-channel leakage.
3Loss of energy
If source and drain junction depths are decreased to suppress sub-surface leakage currents, then static power consumption is reduced, but parasitic series resistance increases and on-current decreases
Solution Approach 1:
The source and drain regions are segmented into first and second sections with different doping concentrations and depths. The first section has higher doping and greater depth to reduce parasitic resistance, while the second section has lower doping and shallower depth to suppress sub-surface leakage. This segmentation enables simultaneous reduction of both parasitic resistance and sub-surface leakage.
4Productivity
If MOSFET dimensions are scaled down to improve cost and performance, then device density and speed are improved, but device performance becomes highly sensitive to dimensional variation
Solution Approach 1:
Different sections of the MOSFET channel are given different doping concentrations and structural properties. This local quality variation makes the device performance less sensitive to dimensional variations in any single section, as the segmented structure provides multiple pathways for current flow and distributes the impact of manufacturing variations across different regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-performance, low-static-power, and low-variability sub-100 nm MOSFET production by balancing on-current and leakage current, while maintaining consistent performance across devices.
Implementation Method 1
A high net dopant concentration in the channel region serves to confine the drain-induced lateral electric field to the drain region, and thereby minimizes the effect of drain bias on the electric potential in the channel region near to the source
Implementation Method 2
by increasing the capacitive coupling between the gate electrode and the channel region (e.g., by decreasing the thickness of the gate dielectric), dominant control over the channel potential (i.e., controlling whether the transistor is on or off) is maintained by the gate electrode rather than the drain, thereby allowing the gate-induced electric field to more effectively suppress source-to-drain leakage current
Data Source
AI summary
By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.