Sealed-Sidewall Device Die for CMOS Image Sensor Debris Containment
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Solution Overview
Problem
The high-volume fabrication of CMOS image sensors through wafer-level processes often results in debris adherence to pixel top surfaces during the dicing process, leading to contamination and reduced manufacturing yield.
Innovation Solution
A method involving the formation of deeply-grooved device wafers with grooves that penetrate each layer, followed by masking and filling these grooves with a sealant, such as solder mask or polyimide materials, to create sealed-sidewall device dies that trap debris and prevent contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level dicing is used to separate individual dies, then high-volume fabrication efficiency is improved, but debris is generated that adheres to pixel top surfaces causing contamination
Solution Approach 1:
The patent applies preliminary action by forming protective sidewall structures and applying sealant materials to the sidewalls of device grooves before the dicing process. This pre-protection ensures that when dicing occurs and generates debris, the contaminants are trapped by the sealed grooves and cannot reach the pixel top surfaces, thus maintaining high fabrication volume while preventing contamination.
Solution Approach 2:
The patent introduces an intermediary protective mechanism by creating sidewall sealants that act as a barrier between the dicing debris and the pixel top surfaces. The sealant material fills the grooves and creates a containment structure that mediates the interaction between harmful debris and sensitive pixel surfaces, allowing high-volume dicing to proceed without contamination.
2Reliability
If grooves are formed deeply to penetrate each layer for sealing, then debris containment is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the sealing function into discrete components: grooves are formed to penetrate specific layers, and sealant materials are applied to the sidewalls of these grooves. This segmentation allows the sealing function to be implemented in a systematic, repeatable manner across the wafer, achieving reliable debris containment while managing manufacturing complexity through modular process steps.
Data Source
AI summary
A method for fabricating a sealed-sidewall device die may include filling grooves of a deeply-grooved device wafer with a sealant, yielding a sealed grooved device wafer. The method may also include forming grooves in a device wafer to yield the deeply-grooved device wafer. The step of forming grooves may include forming a groove that at least partially penetrates each layer of the device wafer. The method may further include masking each device of the deeply-grooved device wafer. A sealed-sidewall device die may include at least one layer including a device substrate layer, a sidewall including a respective surface of each layer of the at least one layer, a sidewall sealant covering the sidewall, and a device formed on the device substrate layer. The sidewall sealant optionally does not cover a top surface of the device. The top surface of the device may directly adjoin an ambient medium thereabove.