Selective SOI Formation via Porous Silicon and ALD
Solution Overview
Problem
Existing methods for manufacturing semiconductor-on-insulator (SOI) structures are limited in reliability and scalability, as they either restrict the formation to full-plate structures or fail to achieve extended SOI areas with high precision.
Innovation Solution
A method involving the formation of a porous silicon layer on a single-crystal silicon surface, followed by deposition of an insulating material like HfO2 using ALD, and subsequent epitaxial growth of a semiconductor layer, allowing for the creation of semiconductor-on-insulator structures with controlled thickness and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gluing method with two silicon wafers is used, then full-plate SOI structures can be formed reliably, but the method is limited to full-plate structures only and cannot position SOI areas selectively
Solution Approach 1:
The invention divides the silicon wafer into distinct regions: a first area with SOI structure and a second area without SOI structure. This segmentation allows selective formation of SOI areas rather than requiring full-plate coverage, resolving the contradiction between reliability of full-plate formation and adaptability for selective positioning.
Solution Approach 2:
The patent applies different treatments to different areas of the silicon wafer: the first area undergoes porous layer formation and epitaxial growth to create SOI structure, while the second area remains as bulk silicon. This local differentiation enables selective SOI area formation with controlled properties in specific regions.
2Adaptability or versatility
If silicon epitaxy is performed on an insulator layer with opening to form SOI areas, then positioning is enabled, but the method is not very reliable and does not enable obtaining extended SOI areas
Solution Approach 1:
The invention performs preliminary actions by first forming a porous silicon layer on the selected area before performing epitaxial growth. This preparatory step creates a template that guides subsequent crystal growth, improving reliability by ensuring proper nucleation and growth conditions are established beforehand.
Solution Approach 2:
The patent changes the physical and chemical parameters of the silicon layer by creating a porous structure with controlled porosity and thickness. This parameter modification enables better control over epitaxial growth, leading to more reliable formation of extended SOI areas compared to direct epitaxy on insulator.
3Manufacturing precision
If electrochemical etching is used to form porous silicon layer, then controlled porous structure is obtained, but the process adds complexity to the manufacturing steps
Solution Approach 1:
The invention replaces mechanical or chemical etching methods with electrochemical etching to form the porous silicon layer. This substitution enables precise control over porous structure formation through electrical parameters (current density, time, electrolyte composition), achieving manufacturing precision while the process integration reduces overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the precise positioning and formation of semiconductor-on-insulator structures on silicon wafers, providing stable high-temperature resistance and controlled semiconductor layer growth, with the ability to create various semiconductor materials like silicon, germanium, and silicon-germanium on-insulator areas.
Implementation Method 1
the porous silicon layer is formed by electrochemical etching of the single-crystal silicon surface
Implementation Method 2
the insulating material is HfO2 or another insulator that can be deposited by a so-called ALD (Atomic Layer Deposition) deposition method
Implementation Method 3
growing by epitaxy a semiconductor layer
Data Source
AI summary
A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.