SHE-MRAM Array Subgrouping via Transistor Segmentation
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Solution Overview
Problem
SHE-MRAM devices require high voltage due to the high electrical resistivity of materials with large spin orbit interactions, necessitating a reduction in current flow distance to avoid excessive voltage application.
Innovation Solution
Incorporating multiple pairs of transistors to divide memory cells into column groups, reducing the length current must flow through high-resistivity second leads, thereby minimizing voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current flows through the entire length of the second lead to switch memory cells, then all memory cells can be accessed, but excessive voltage is applied due to high electrical resistivity
Solution Approach 1:
The patent divides the memory cell array into multiple subgroups using additional word lines. Each subgroup can be independently accessed, allowing current to flow through shorter segments of the second lead rather than the entire length. This segmentation reduces the effective resistance path and consequently lowers the voltage requirement while maintaining full memory cell accessibility through selective subgroup activation.
2Quantity of substance
If the second lead is made thinner to increase storage density, then storage density improves, but electrical resistivity increases requiring higher voltage
Solution Approach 1:
By segmenting the memory array into subgroups with additional word lines, the patent enables independent access to smaller portions of the memory array. This allows thinner second leads to be used within each subgroup, maintaining high storage density while limiting the current path length and reducing the cumulative resistance, thereby lowering the voltage requirement for switching.
Solution Approach 2:
The patent applies different structural configurations to different regions of the memory device. Within each subgroup, the second lead can be optimized for local density requirements, while the overall array structure accommodates multiple subgroups with independent access paths. This local optimization allows thinner leads in high-density regions without compromising the electrical performance of the entire device.
3Length of stationary object
If the layer with large spin orbit interactions is made thinner to reduce resistance, then resistance decreases, but voltage still remains high due to material properties
Solution Approach 1:
The patent segments the memory cell array into multiple subgroups accessed via additional word lines, which divides the current path into shorter segments. Even though the layer with large spin orbit interactions remains thin to maintain low resistance, the segmentation further reduces the total resistance by limiting the length of the current path through high-resistivity materials, thereby reducing the voltage requirement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for efficient current flow through a shorter portion of the high-resistivity leads, reducing the voltage needed to switch memory cells and enhancing the operational efficiency of SHE-MRAM devices.
Implementation Method 1
One type of MRAM is Spin Hall Effect MRAM (SHE-MRAM). SHE-MRAMs devices contain memory elements formed from two magnetically polarized layers, each of which can maintain a magnetic polarization field, separated by a thin insulating layer, which together form a magnetic tunnel junction (MTJ) stack. A layer having large spin orbit interactions may be in contact with the MTJ stack, and Spin Hall Effect is used to switch the MTJ stack as a current flows through the layer.
Data Source
AI summary
Embodiments of the present disclosure generally relate to data storage systems, and more particularly, to a SHE-MRAM device. The SHE-MRAM device includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads. The second leads are made of a material having large spin orbit interactions and high electrical resistivity. The SHE-MRAM device further includes a periphery circuitry having multiple pairs of transistors. The multiple pairs of transistors reduce the length a current has to flow through a second lead of the plurality of second leads. By limiting the distance a current can flow through the second lead, applying excessive voltage to the second lead is avoided.