Metal Gate Electrodes for 3D Nonvolatile Memory
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Solution Overview
Problem
Current three-dimensional nonvolatile memory devices face challenges in reducing gate electrode resistance and preventing process defects, which affect their operation speed and reliability.
Innovation Solution
The solution involves a three-dimensional nonvolatile memory device design with gate electrodes made of metal material, including a first gate electrode in the memory cell region and a second gate electrode in the contact region, connected by supporters, and a method for fabricating these devices by stacking gate conductive and dielectric layers, etching to form the first gate electrodes, and filling with metal to form the second gate electrodes, thereby reducing resistance and preventing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate electrodes are made of conventional material in three-dimensional nonvolatile memory devices, then manufacturing process is simpler, but gate electrode resistance is high which reduces operation speed
Solution Approach 1:
The patent changes the material parameter of gate electrodes from conventional polysilicon to metal materials (such as tungsten, aluminum, or copper), fundamentally altering the electrical resistance characteristic. This material substitution directly reduces gate electrode resistance, enabling faster operation speeds in three-dimensional nonvolatile memory devices while maintaining manufacturing feasibility through established metal deposition techniques.
2Manufacturing precision
If gate conductive layers are removed from contact region to form first gate electrodes, then memory cell structure is defined, but process defects may occur during etching
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary element between the gate conductive layer and the final gate electrode structure. This sacrificial layer facilitates controlled removal of gate conductive layers from the contact region through selective etching, preventing direct damage to underlying structures and reducing process defects while maintaining precise gate electrode formation in the memory cell region.
Solution Approach 2:
The patent applies different processing conditions to different regions: the contact region undergoes selective gate conductive layer removal to form openings, while the memory cell region retains the gate conductive layers as first gate electrodes. This localized quality approach ensures precise structural definition in the memory cell region while enabling proper contact formation in the contact region, minimizing cross-contamination and process defects.
3Speed
If metal material is used to form second gate electrodes in contact region, then resistance is reduced and operation speed improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the gate electrode structure into two distinct parts: first gate electrodes in the memory cell region made from gate conductive layers, and second gate electrodes in the contact region made from metal materials. This segmentation allows each region to be optimized independently - the memory cell region maintains simpler polysilicon-based structures while the contact region benefits from low-resistance metal electrodes, overall reducing device complexity compared to using metal throughout.
Solution Approach 2:
The patent performs preliminary formation of the stack structure with gate conductive layers and dielectric layers before selectively removing gate conductive layers from the contact region. This preliminary action establishes a well-defined template that guides subsequent metal filling, ensuring precise alignment and reducing manufacturing complexity by avoiding complex alignment steps that would be required if metal electrodes were formed without the gate conductive layer template.
Data Source
AI summary
A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to the semiconductor substrate. The gate electrodes include a first gate electrode and a second gate electrode. The first gate electrode is disposed on the memory cell region to intersect the active pillars. The second gate electrode is disposed on the contact region, connected to the first gate electrode and comprising metal material.