Modular Data Transfer Architecture for SoC Interconnect Bottlenecks
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Solution Overview
Problem
The global bus architecture for intra-chip data communication in System on Chip (SoC) devices becomes a bottleneck as the number of computational blocks increases, leading to reduced speed performance due to increased complexity and interconnect delays.
Innovation Solution
A modular data transfer architecture using interconnected communication tiles with pipelining structure, where each tile has initiator and target ports, and a port mapper translates global addresses to local addresses for efficient data routing, reducing arbitration and interconnect delays by localizing these processes within each tile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a global bus architecture is used for data transfer, then data communication between computational blocks is enabled, but the architecture becomes a bottleneck for speed performance as the number of blocks increases
Solution Approach 1:
The global bus architecture is segmented into multiple hierarchical levels: a global arbitration unit that manages high-level access decisions and local data steering units that handle low-level data routing. This segmentation allows the system to maintain comprehensive data communication capability while reducing the bottleneck effect by distributing the arbitration and steering functions across multiple levels rather than a single centralized unit.
2Adaptability or versatility
If the number of computational blocks increases, then system functionality is enhanced, but the complexity of the arbitration unit and data steering unit scales with n
Solution Approach 1:
The arbitration function is segmented into a global arbitration unit that handles system-wide access decisions and local data steering units that manage individual block communications. This segmentation reduces the complexity scaling by distributing the n x n arbitration requirements across multiple smaller units, each handling a subset of the arbitration tasks.
Solution Approach 2:
Local data steering units act as intermediaries between the global arbitration unit and the computational blocks. These intermediaries handle the detailed data routing and steering operations locally, reducing the burden on the global arbitration unit and preventing complexity from scaling linearly with the number of blocks.
3Adaptability or versatility
If a global bus architecture is used, then data transfer between any initiator and target is supported, but interconnect delays increase with the area of the SoC
Solution Approach 1:
The data steering function is segmented into local data steering units positioned near the computational blocks. This segmentation allows data to be steered and routed locally within smaller interconnect regions rather than traversing the entire global bus across the whole SoC area, significantly reducing interconnect delays while maintaining comprehensive connectivity.
Solution Approach 2:
Local data steering units provide localized data steering capability near each computational block, enabling fast local data transfers without requiring data to traverse the entire global interconnect. This local quality approach reduces interconnect delay by keeping data routing decisions and execution close to the source and destination blocks.
Data Source
AI summary
A system on chip (SoC) integrated circuit includes a plurality of computational blocks. A modular data transfer architecture interconnects the computational blocks for intra-chip communications. The computational blocks include an initiator block and a target block, with the initiator block originating a data communication having a global address associated with the target block. The modular data transfer architecture includes a first peripheral module having an initiator port connected to the initiator block to receive the data communication and a second peripheral module having a target port connected to the target block. A first port mapper within the first peripheral module maps the global address to a first peripheral module target port along a data path towards the second peripheral module. A second port mapper within the second peripheral module maps the global address to the target port connected to the target block. The modular data transfer architecture further includes a plurality of internal modules support intra-chip communications. Each internal module has a plurality of initiator ports connected to target ports of other modules and a plurality of target ports connected to initiator ports of other modules. An internal port mapper for each internal module maps the global address to a certain internal module target port along the data path towards the second peripheral module.