Non-volatile Memory Read Speed via Reference Cell Resistance Matching
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Solution Overview
Problem
Conventional non-volatile semiconductor memory devices face challenges in achieving high-speed reading due to resistance variations in the inversion layer, which affect the matching of time constants between the main cell and reference cell global bit lines, resulting in reduced read margins and inability to perform high-speed reading.
Innovation Solution
The non-volatile semiconductor memory device includes sense amplifiers that amplify the potential difference between a main cell array and a reference cell array, with the main cell array comprising select gates, common sources, word lines, and storage nodes, and the reference cell array configured to match the resistance and capacitance of the main cell array, allowing for precise voltage application and current path configuration to reduce current variations during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional non-volatile semiconductor memory devices use inversion layers for current paths, then the device structure is simple and easy to manufacture, but resistance variations in the inversion layer cause mismatched time constants between main cell and reference cell global bit lines, reducing read margins and preventing high-speed reading
Solution Approach 1:
The patent changes the resistance parameter of the current path by replacing the inversion layer with a dedicated resistance element having a controlled resistance value. This allows precise matching of time constants between main cell and reference cell global bit lines, enabling both high-speed reading and maintained read margins through parameter optimization rather than relying on variable inversion layer resistance
Solution Approach 2:
The patent introduces a dedicated resistance element as an intermediary component between the common source and the global bit line. This intermediary element provides stable, controllable resistance to match time constants, eliminating the reliability issues caused by inversion layer resistance variations while maintaining the simple device structure
2Reliability
If the inversion layer resistance is used for current paths in main cell and reference cell, then the device complexity is low, but the resistance variations prevent matching of time constants, resulting in reduced read margins
Solution Approach 1:
The patent creates a copied current path structure for the reference cell that mirrors the main cell configuration, including identical resistance elements. This copying approach ensures matched time constants and read margins while maintaining simplicity through structural symmetry rather than requiring complex compensation circuits
3Productivity
If conventional reading operations are performed with inversion layers, then the manufacturing process is simple, but resistance variations cause current path mismatch, preventing high-speed reading
Solution Approach 1:
The patent implements self-service by having each current path (main cell and reference cell) include its own dedicated resistance element that automatically provides the necessary resistance value. This eliminates the need for complex external matching circuits or adjustment mechanisms, maintaining ease of manufacture while enabling high-speed reading through inherent path matching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed reading by matching the capacitance and resistance values of the current paths in both the main and reference cells, reducing current variations and increasing read margins, thereby enabling faster data retrieval.
Implementation Method 1
sense amplifiers each for amplifying a potential difference between a main cell array and a reference cell array
Implementation Method 2
by applying a positive voltage to the select gate 103, an inversion layer 120 is formed on the surface of the substrate 101 below the select gate 103 in the cell regions
Implementation Method 3
The floating gates 106 are storage nodes, and are disposed between the first diffusion regions 107 and the select gates 103, respectively via the insulating film 102
Data Source
AI summary
Disclosed is to enable high speed reading from a storage node when a read is executed. A main cell array is constituted from main cell division units 20a. Each main cell division unit 20a includes select gates SG that extend in a vertical direction, common sources CS that extend in a horizontal direction below the select gates SG outside a cell region, word lines W0 to W15 that extend above the select gates SG in the horizontal direction within the cell region, a plurality of storage nodes disposed in the vicinity of intersecting portions between the word lines W0 to W15 and the select gates SG, respectively, below the word lines W0 to W15, and a bit line MGB for transmitting to a sense amplifier 11 information on one of the storage nodes through a selection switch 21. In the main cell division unit 20a, an inversion layer is formed below each of the select gates SG within the cell region by applying a positive voltage to each of the select gates SG. A reference cell array is constituted from a reference cell division unit 30a having a same configuration as the main cell division unit 20a.