Vertical Silicon Channel Phase Transition for Conductivity
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Solution Overview
Problem
The increasing integration of semiconductor structures necessitates reduced critical dimensions, complicating manufacturing and affecting electrical performance, with existing technologies failing to achieve improved electrical performance effectively.
Innovation Solution
A method involving the formation of a silicide layer and a vertical Si channel layer, followed by a first annealing step to change the solid phase of the Si channel layer from a lower conductivity amorphous or polysilicon phase to a higher conductivity single-crystal-like silicon phase, creating a semiconductor structure with improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the critical dimension of semiconductor structures is decreased to achieve increasing integration, then device density and integration level are improved, but manufacturing complexity increases and electrical performance deteriorates
Solution Approach 1:
The patent applies parameter changes by transforming the silicon channel layer from amorphous/polycrystalline state to single-crystal state through controlled annealing processes. This phase transformation changes the electrical parameters (conductivity, mobility) of the semiconductor material, enabling improved electrical performance at scaled dimensions without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent utilizes phase transitions of silicon material during annealing steps, where the silicon channel layer transitions from amorphous or polycrystalline phase to single-crystal phase. This phase transition fundamentally alters the electrical properties of the channel layer, providing a mechanism to maintain or improve electrical performance as device dimensions are reduced
2Quantity of substance
If the critical dimension of semiconductor structures is decreased to achieve increasing integration, then device density is improved, but electrical performance deteriorates
Solution Approach 1:
The patent changes the crystallographic parameter of the silicon channel layer from amorphous/polycrystalline to single-crystal structure through annealing. This parameter change directly improves electrical performance metrics such as carrier mobility and conductivity, counteracting the negative effects of dimension reduction on electrical performance
Solution Approach 2:
The patent creates a composite structure with distinct material phases: a single-crystal silicon channel layer formed on top of an amorphous or polycrystalline silicon layer. This composite approach allows the device to benefit from the ease of fabrication of amorphous/polycrystalline silicon while achieving the superior electrical performance of single-crystal silicon in the active channel region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances electrical performance by increasing conductivity and reducing electrical resistance, achieving better cell current and defect density characteristics comparable to single-crystal silicon.
Implementation Method 1
change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase
Implementation Method 2
Performing a first annealing step so as to move the silicide layer upward and change a solid phase
Data Source
AI summary
A semiconductor structure and a method for manufacturing the same are provided. The method includes: forming a silicide layer, forming a vertical Si channel layer, wherein the vertical Si channel layer is on an upper surface of the silicide layer, the vertical Si channel layer has a first silicon phase; performing a first annealing step so as to move the silicide layer upward and change a solid phase of the vertical Si channel layer from the first silicon phase to a second silicon phase at an interface of the silicide layer and the vertical Si channel layer, wherein the second silicon phase has a conductivity higher than a conductivity of the first silicon phase.