Semiconductor Storage Node Contact Resistance via Metal Silicide
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Solution Overview
Problem
As semiconductor devices become highly integrated with decreasing design rules, there is a challenge in maintaining sufficient capacitance in a small area, particularly for DRAMs with stack type capacitors, where the storage node electrode height increases, requiring effective surface area enhancement without compromising contact resistance and device speed.
Innovation Solution
A fabricating method involving the formation of an interlayer insulation layer, an etch stop layer, and a molding insulation layer, followed by selective etching to expose the etch stop layer, conformal deposition of a conductive layer, and annealing to form a metal silicide pattern, which enhances the contact area between the storage node contact plug and electrode, reducing contact resistance and maintaining capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the storage node electrode height is increased to obtain desired capacitance in a small area, then the effective surface area of the storage electrode increases, but the contact resistance between the storage node contact plug and electrode increases
Solution Approach 1:
The contact area is segmented into multiple regions by forming a metal silicide pattern in specific areas of the etch stop layer. This segmentation allows the contact interface to be divided into high-resistance and low-resistance regions, with the silicide pattern providing enhanced conductive pathways that reduce overall contact resistance while maintaining the increased electrode height for sufficient capacitance.
Solution Approach 2:
The metal silicide pattern is formed in predetermined areas of the etch stop layer to create localized regions of improved electrical contact. This local quality enhancement ensures that the critical contact areas between the storage node contact plug and electrode have reduced resistance, while other areas maintain their structural functions.
2Area of stationary object
If the design rule is decreased to increase integration level, then the unit cell area decreases, but maintaining sufficient capacitance becomes more difficult
Solution Approach 1:
The solution moves from a two-dimensional contact area to a three-dimensional contact structure by forming the metal silicide pattern within the etch stop layer. This vertical dimensionality change allows increased contact area and reduced resistance without increasing the lateral footprint, enabling sufficient capacitance maintenance in reduced unit cell areas achieved through decreased design rules.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively increases the contact area between the storage node contact plug and electrode, reducing resistance and ensuring stable capacitance in densely integrated semiconductor devices, thereby improving device performance and speed.
Implementation Method 1
annealing the first conductive layer and the etch stop layer. The annealing may be performed by a rapid thermal nitridation (RTN) process under a nitrogen (N2) atmosphere at a temperature in a range of about 500° C. to about 900° C.
Implementation Method 2
The annealing may be performed by a rapid thermal nitridation (RTN) process under a nitrogen (N2) atmosphere at a temperature in a range of about 500° C. to about 900° C.
Data Source
AI summary
A fabricating method of a semiconductor device includes forming an interlayer insulation layer on a substrate, the interlayer insulation layer including a storage node contact plug, forming an etch stop layer on the interlayer insulation layer, the etch stop layer including a silicon layer or a silicon germanium layer, forming a molding insulation layer on the etch stop layer, forming a hole in the molding insulation layer by selectively etching the molding insulation layer until a portion of the etch stop layer is exposed, forming a first conductive layer conformally on an inner surface of the hole and on a top surface of the molding insulation layer, and forming a metal silicide pattern in a predetermined area of the etch stop layer exposed by the molding insulation layer by annealing the first conductive layer and the etch stop layer.