Semiconductor Solder Pad Compression Bonding
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Solution Overview
Problem
Conventional semiconductor devices face challenges with weak bonding strength between solder pads and chip pads due to isotropic etching in wet etching processes, leading to reliability issues and increased costs associated with dry etching techniques, while requiring compact size and low profile designs.
Innovation Solution
A semiconductor device and fabrication method involving the formation of solder pads on a substrate using wet etching, followed by embedding these pads into connection bumps on a semiconductor chip through compression at a temperature below their melting points, creating a concave-convex structure that enhances bonding strength and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wet etching process is used to form solder pads, then fabrication cost is reduced and fabrication speed is increased, but bonding strength between solder pads and connection bumps is reduced
Solution Approach 1:
The patent applies preliminary action by forming a convex structure on the solder pad surface before the bonding process. This pre-formed convex structure serves as a mechanical interlock feature that will engage with the connection bump during compression, thereby enhancing bonding strength while still using the cost-effective wet etching process.
Solution Approach 2:
The patent employs composite materials by combining the metal solder pad layer with a convex structural feature. This composite approach creates a multi-functional solder pad that provides both electrical conductivity and enhanced mechanical bonding capability, resolving the contradiction between fabrication efficiency and bonding strength.
2Ease of manufacture
If wet etching process is used to form solder pads, then fabrication cost is reduced, but etching selectivity is poor
Solution Approach 1:
The patent applies local quality by creating a convex structure at specific locations on the solder pad surface. This localized structural modification enhances bonding performance only where needed (at the contact interface with connection bumps) while maintaining the overall simplicity and low cost of the wet etching fabrication process.
3Loss of time
If metal layer thickness is reduced to reduce etching time, then etching rate is increased, but reliability of circuitry is reduced
Solution Approach 1:
The patent applies dimensionality change by transitioning from a flat, two-dimensional solder pad surface to a three-dimensional convex structure. This vertical dimension addition provides enhanced bonding capability and mechanical interlock without requiring increased metal layer thickness, thereby maintaining circuitry reliability while reducing etching time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method increases the bonding strength between the substrate and semiconductor chip, improves fabrication reliability, and allows for the use of thicker metal layers, overcoming the limitations of thin metal layers in wet etching and avoiding the costs and selectivity issues of dry etching.
Implementation Method 1
The wet etching process employs a strong acid or strong alkali etchant to perform a chemical reaction on surface molecules on a metal layer to be etched by diffusion effect
Implementation Method 2
compressing the substrate and the semiconductor chip toward each other at a temperature of the compression between the connection bumps and the solder pads lower than the melting points of the solder pads and the connection bumps, such that the solder pads are embedded into the connection bumps
Data Source
AI summary
A semiconductor device and a method of manufacturing the same are disclosed. The method is carried out by forming solder pads on a substrate by wet etching, flipping a semiconductor chip having a plurality of connection bumps formed on an active surface of the semiconductor chip for the connection bumps to be mounted by compression on the solder pads of the substrate correspondingly, at a temperature of the compression between the connection bumps and the solder pads lower than the melting points of the solder pads and the connection bumps, so as to allow the semiconductor chip to be engaged with and electrically connected to the substrate through the connection bumps and the solder pads, thereby enhancing the bonding strength of the solder pads and the connection bumps and increasing the fabrication reliability.