3D Memory Device With III-V Compound Semiconductor Channel

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Solution Overview

Problem

Current three-dimensional memory devices face challenges in achieving high-density storage with efficient III-V compound semiconductor channel and source/drain contacts, particularly in forming reliable memory opening fill structures with graded III-V compound semiconductor materials.

Innovation Solution

A three-dimensional memory device is developed with a III-V compound semiconductor channel and source/drain contacts, featuring a substrate with an alternating stack of insulating and electrically conductive layers, where memory openings are filled with a III-V compound semiconductor pedestal, channel, and graded drain region, enabling efficient conductivity and storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional silicon-based materials are used for channel and contacts in 3D memory devices, then manufacturing process is well-established, but storage density and conductivity are insufficient for ultra-high-density requirements

Engineering Contradiction:
Improvestorage density and conductivityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the material composition parameters by introducing III-V compound semiconductors (such as GaAs, InGaAs) with specific bandgap properties and doping characteristics. The graded composition (e.g., InxGa1-xAs with varying x) allows continuous adjustment of material parameters to optimize both conductivity and storage density while managing lattice mismatch through compositional grading.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures including alternating stacks of insulating layers and electrically conductive layers, combined with graded III-V compound semiconductor layers. This composite approach integrates materials with different properties (insulating, conductive, semiconducting) to achieve both high storage density and efficient conductivity while managing manufacturing complexity.

Inventive Principle:
Principle #40Composite materials

2Reliability

If graded III-V compound semiconductor materials are used in drain regions, then conductivity and carrier mobility are improved, but material composition control and manufacturing precision are more challenging

Engineering Contradiction:
Improveconductivity and carrier mobilityVSAvoidcompositional gradient control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating spatially varying material compositions within the drain region. The graded III-V compound semiconductor (e.g., InxGa1-xAs) has composition that changes locally from one region to another, providing position-dependent properties: higher In content near the channel for high mobility, and lower In content toward the contact for better ohmic contact, thus achieving both improved conductivity and manageable manufacturing precision through localized property optimization.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11374020B2Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
Publication Date: 2022.06.28 SANDISK TECHNOLOGIES LLC
  • US11374020B2 patent drawing
  • US11374020B2 patent drawing
  • US11374020B2 patent drawing

AI summary

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.