3D Semiconductor Memory Device Well Pickup Regions
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face challenges in achieving uniform operating characteristics when memory cells are stacked vertically, leading to integration density issues.
Innovation Solution
The implementation of stacked structures with vertical semiconductor patterns, common source regions, and well pickup regions on a semiconductor layer, where the well pickup regions are electrically connected to a voltage generator to receive an erase voltage, ensuring uniform voltage application across the cell array structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase integration density, then integration density is improved, but uniformity of operating characteristics deteriorates
Solution Approach 1:
The patent divides the semiconductor layer into multiple independent well pickup regions positioned at different vertical levels. Each well pickup region is independently doped and controlled, allowing separate voltage application to different segments of the stacked memory cells. This segmentation enables uniform erase voltage distribution across vertically stacked cells, resolving the uniformity issue while maintaining high integration density.
Solution Approach 2:
The patent implements localized doping regions (well pickup regions) at specific positions within the semiconductor layer, creating non-uniform local properties. These locally doped regions have different conductivity types and are positioned to interact with specific stacks of memory cells, providing tailored voltage compensation for each local area. This local quality approach ensures uniform operating characteristics across the entire device while maintaining vertical stacking for high density.
2Manufacturing precision
If well pickup regions are added to provide uniform erase voltage, then uniformity of erase operation is improved, but device complexity increases
Solution Approach 1:
The patent merges the well pickup regions directly into the semiconductor layer structure, combining multiple functions into a single integrated component. The well pickup regions serve both as voltage application points and as part of the overall device architecture, eliminating the need for separate external voltage distribution structures. This merging approach provides uniform erase operation while minimizing additional structural complexity.
Solution Approach 2:
The well pickup regions are designed to serve multiple functions: they provide erase voltage to vertically stacked memory cells, act as part of the semiconductor layer structure, and enable independent voltage control for uniformity. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in device complexity while achieving uniform erase operation across stacked cells.
Data Source
AI summary
A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.