Non-Volatile Memory Coupling Ratio via Vertical Recess Structure
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Solution Overview
Problem
Non-volatile memory devices often have a low coupling ratio, which affects electron flowing efficiency during programming and erasing operations, leading to reduced work efficiency.
Innovation Solution
A method for manufacturing a non-volatile memory that involves forming a trench in a substrate, creating an isolation structure, removing a portion of it to form a recess, and filling the recess with conductive layers to increase the overlap area between the floating gate and control gate, thereby enhancing the coupling ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the coupling ratio is increased by conventional methods (increasing overlap area, reducing dielectric thickness, or increasing dielectric constant), then the coupling ratio improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent introduces a recess structure that extends vertically into the substrate beneath the isolation structure, creating a third-dimensional space for the conductive layer. This vertical dimension allows the control gate to extend underneath the floating gate, increasing the overlap area and coupling ratio without requiring larger lateral dimensions or thinner dielectric layers, thus avoiding increased device complexity
Solution Approach 2:
The conductive layer forming the control gate is nested within the recess structure, which is itself formed within the substrate beneath the isolation structure. This nesting arrangement allows the control gate to be positioned in a previously unused vertical space, increasing the effective overlap area with the floating gate without adding lateral complexity to the device structure
2Productivity
If the coupling ratio is increased to improve electron flowing efficiency, then the work efficiency improves, but the manufacturing process complexity increases
Solution Approach 1:
The recess structure is formed in the substrate before the floating gate and control gate are fabricated. This preliminary action creates the vertical space needed for the control gate to extend underneath the floating gate, enabling increased coupling ratio and electron flowing efficiency before the actual gate structures are built, thus managing manufacturing complexity through staged process planning
3Reliability
If larger floating and control gates are formed to increase overlap area, then the coupling ratio improves, but the area occupied by each device increases
Solution Approach 1:
Instead of increasing the lateral dimensions of the gates to achieve larger overlap area, the patent utilizes the vertical dimension by creating a recess and extending the control gate underneath the floating gate. This three-dimensional arrangement increases the effective overlap area while maintaining compact lateral device footprint, thus improving coupling ratio without increasing device area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method increases the coupling ratio and improves the operational efficiency of the non-volatile memory by allowing larger floating and control gates, enhancing electron flow efficiency during programming and erasing operations.
Implementation Method 1
the method of removing a portion of the isolation structure includes performing a wet etching process, for example
Implementation Method 2
the method of forming the first dielectric layer includes performing a thermal oxidation process, for example
Data Source
AI summary
A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.