Vertical Channel TFET Flash Memory for High Efficiency
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Solution Overview
Problem
Conventional flash memory technologies face challenges in programming efficiency, power consumption, and inhibiting the punch-through effect, especially as feature sizes are scaled down, due to limitations in their basic physical mechanisms.
Innovation Solution
A flash memory structure utilizing vertical channels with a tunneling field effect transistor (TFET) and a polysilicon floating gate, where lightly doped silicon substrates are used with specific doping regions and oxide layers to enhance programming efficiency and reduce power consumption, while preventing punch-through effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional flash memory structures (floating gate or discrete trap) are used, then the basic storage function is achieved, but programming efficiency is low and power consumption is high
Solution Approach 1:
The patent changes the fundamental physical mechanism from thermal injection to quantum tunneling by modifying the energy band structure parameters. By creating a TFET with specific doping configurations (P+ source, N- channel, N+ drain) and applying appropriate gate voltages, the energy bands are bent to enable direct band-to-band tunneling, achieving significantly higher programming efficiency and lower power consumption
Solution Approach 2:
The patent replaces the conventional thermal injection mechanism with a quantum mechanical tunneling mechanism. The TFET structure utilizes quantum tunneling through the band barrier formed by the P+ source and N- channel interface, fundamentally changing the physical process from thermal to quantum-based electron injection into the floating gate
2Productivity
If feature size is scaled down to increase storage density, then more memory cells can be integrated, but punch-through effect increases
Solution Approach 1:
The patent employs a composite doping structure with multiple doping regions (P+ source, N- channel, N+ drain) and different oxide layers (tunneling oxide, block oxide, sidewall oxide) to create a complex energy band profile. This composite structure enables effective punch-through suppression by forming multiple barriers and controlling carrier transport through the channel
Solution Approach 2:
The patent applies different doping concentrations and oxide thicknesses at different locations within the device. The P+ source region has high doping concentration to create strong band bending, the N- channel has low doping for long depletion region, and the N+ drain has high doping for efficient electron collection. This localized optimization prevents punch-through while maintaining scaling
3Ease of manufacture
If conventional MOS transistor structure is used, then manufacturing is straightforward, but programming efficiency and power consumption are not optimized
Solution Approach 1:
The patent segments the channel region into distinct doping zones (P+ source, N- channel, N+ drain) separated by oxide layers. This segmentation creates independent control regions that can be optimized for their specific functions while maintaining compatibility with standard CMOS fabrication processes
Solution Approach 2:
The patent introduces a vertical dimension to the doping profile with the P+ source region extending vertically to create the tunneling interface. This vertical segmentation enables band-to-band tunneling by creating a steep energy band gradient in the vertical direction, improving programming efficiency while maintaining planar device footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The TFET-based flash memory achieves significantly improved programming efficiency, reduced power consumption, and increased storage density by leveraging band-to-band tunneling and a double-channel structure, outperforming conventional flash memory by 2 to 3 orders of magnitude in programming efficiency and effectively inhibiting punch-through effects.
Implementation Method 1
a transistor based on the quantum tunneling effect
Data Source
AI summary
The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.