Semiconductor Memory Select Gate Segmentation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing power consumption while maintaining high memory density and efficient operation, particularly in three-dimensionally stacked memory cell configurations, where the formation of memory trenches and replacement processes can lead to increased power usage and potential faults.
Innovation Solution
The semiconductor memory device employs a configuration where the conductive layer is divided by slits to allow for independent control of select gate lines for each block, reducing power consumption and preventing faults by maintaining an etch stopper for processing memory trenches, replacement holes, and memory pillars, while enabling block-by-block control of select gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory trenches and replacement holes are formed in three-dimensionally stacked memory cell configurations to increase memory density, then memory density is improved, but power consumption increases
Solution Approach 1:
The conductive layer is divided into multiple independent select gate lines (first select gate line, second select gate line, third select gate line) corresponding to different blocks (first block, second block, third block). This segmentation allows independent control of each block, enabling power consumption reduction by activating only the required blocks during operation while maintaining high memory density through the three-dimensional stacked configuration.
2Use of energy by moving object
If conductive layers are divided by slits to enable block-by-block control of select gate lines, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The conductive layer is segmented into multiple select gate lines by slits, allowing independent block control and reduced power consumption. The slits create distinct electrical regions that can be independently addressed, enabling the system to activate only necessary blocks rather than the entire memory array.
Solution Approach 2:
The conductive layer serves multiple functions: it acts as a continuous structure for structural integrity, gets divided by slits for independent block control, and maintains etch stopper functionality for processing memory trenches, replacement holes, and memory pillars. This multi-functionality reduces the need for additional separate structures.
3Manufacturing precision
If etch stopper is maintained for processing memory trenches, replacement holes, and memory pillars, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The conductive layer serves as an etch stopper during the formation of memory trenches, replacement holes, and memory pillars, ensuring precise manufacturing. Simultaneously, it functions as a continuous structural element and gets divided into selective gate lines, eliminating the need for separate etch stopper layers and reducing overall device complexity.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a substrate, first to eleventh conductive layers, first and second pillars, and first to fourth insulating regions. The first insulating regions are provided between the third and fifth conductive layers and between the fourth and sixth conductive layers. The second insulating regions are provided between the eighth and tenth conductive layers and between the ninth and eleventh conductive layers. The third insulating region is provided between the third to sixth conductive layers and the eighth to eleventh conductive layers. The fourth insulating region is provided between the second and seventh conductive layers. The fourth insulating region is separated from the third insulating region in a planar view.