3D Memory Local Column Decoding for Concurrent Sub-Page Access
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Solution Overview
Problem
Traditional memory devices face challenges in efficiently utilizing three-dimensional architectures to increase memory capacity without expanding footprint, particularly in managing concurrent operations and data access within multi-layered memory structures.
Innovation Solution
A 3D memory device architecture with local column decoding and global data signal buses, incorporating local column decoders and redrivers, allows for concurrent sub-page accesses and interleaved operations, enhancing efficiency and data handling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional single layer architecture with peripheral logic circuitry is used, then device complexity is reduced, but memory capacity and access efficiency deteriorate due to limited footprint utilization
Solution Approach 1:
The patent transitions from a traditional single-layer planar architecture to a three-dimensional stacked architecture where memory cell arrays are arranged in multiple vertical layers. This dimensional change enables increased memory capacity without expanding the horizontal footprint, as multiple layers of memory cells are stacked above the logic circuitry layer, effectively utilizing the vertical space to multiply the storage capacity.
Solution Approach 2:
The patent merges the logic circuitry layer with multiple memory cell array layers into a single integrated three-dimensional structure. The logic circuitry is positioned in a first layer while memory cell arrays are stacked in second and third layers directly above, creating a unified device where supporting logic and storage elements work together in a compact vertical integration rather than separate planar regions.
2Loss of time
If global column decoding is used in 3D memory architecture, then address decoding coverage is complete, but access time increases due to signal propagation delays across multiple layers
Solution Approach 1:
The patent segments the column decoding function into two distinct parts: a global column address decoder that receives the full column address and generates global column select signals, and local column decoders in each memory layer that receive a portion of the column address and generate local column select signals. This segmentation allows parallel decoding operations to occur simultaneously across multiple layers, reducing the overall access time by eliminating sequential signal propagation delays.
Solution Approach 2:
The patent implements preliminary action by having the global column address decoder generate global column select signals in advance, which are then distributed to local column decoders in each memory layer. This preliminary generation of select signals enables the local decoders to begin their decoding operations simultaneously rather than waiting for signals to propagate sequentially through each layer, thereby reducing the total access time for column selection across the stacked memory structure.
3Productivity
If concurrent sub-page accesses are enabled, then operational throughput is improved, but data bus management complexity increases
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of local column decoders and sense amplifier units that act as intermediaries between the global data bus and individual memory layers. These intermediaries receive global column select signals, perform local decoding, and manage data transfer between the global bus and specific memory cell arrays in parallel. This intermediary structure enables concurrent sub-page accesses by coordinating data flow across multiple layers simultaneously, improving throughput while managing bus complexity through hierarchical control.
Data Source
AI summary
A 3D memory device includes a plurality of mats that each include a memory array stacked over logic circuitry supporting operations of the memory array. The logic circuitry include a local column decoder under the memory array for selecting one or more local column select lines associated with a memory operation. The logic circuitry furthermore includes one or more selectable global array data bus redrivers for receiving global data signals from a set of global data signal buses, selecting one of the global data signal buses, and amplifying signals between the selected global data signal bus and a local data signal bus that communicates the data signals to and from the memory array. The 3D memory device supports concurrent sub-page accesses which may be interleaved for efficient memory operations.