Digital Storage TRIZ Cases

Separate sense amplifiers let DRAM split and interrupt refresh phases, reducing bitline interference and preserving access bandwidth.

A conductive shunt links the free layer and capping layer in an MTJ to preserve high PMA while cutting series resistance, set voltage, and power.

Separate SOT-MRAM row groups and opposite write-current directions enable concurrent read and write operations with lower interference.

Shared block MUX activation cuts row decoder area and power in DRAM while reducing leakage current and signal skew.

Multiplexers in the logic chip let stacked memory share package channels, cutting I/Os and wiring while scaling memory capacity.

Conductive spacers add hole carriers to an oxide semiconductor channel, strengthening ferroelectric switching and erase efficiency.

Using strained manganese antiferromagnetic layers with spin Hall torque, this case enables picosecond-class non-volatile memory switching.

Middle strap areas and feedthrough circuits shorten SRAM power paths, improving write voltage and cutting power loss in dense memory macros.

Segmented bit lines across stacked metallization layers cut load and capacitive coupling, enabling denser memory arrays with stable reads and writes.

Different MTJ cell sizes and matched reference resistances improve sensing, write stability, and data retention in variable resistance memory.

Independent local and global clock generation raises DFT test speed in memory circuits without disrupting normal read and write operation.

Vertical memory-cell stacking with a central pad region and shared word lines raises integration density while limiting pad area and wiring complexity.

Local column decoders and selectable bus redrivers enable concurrent sub-page access in stacked 3D memory while easing delay limits.

Hierarchical detectors in a memory controller improve row hammer detection, cut false alarms, and reduce memory and power overhead.

Vertical stacking and side pad-region routing raise memory-cell density while preserving word-line connections in compact semiconductor memory.

A shared page buffer across multiple memory cell arrays cuts peripheral circuit area and supports denser vertical non-volatile memory integration.

Oppositely oriented unipolar selectors enable independent threshold tuning to cut leakage and read/write disturbance in cross-point memory.

A shared read/write line in a vertical 2-transistor memory cell cuts footprint and power dissipation while supporting higher storage density.

Aligned MTJ sidewalls, spacers, and liner integration shrink MRAM cell area while lowering power use and improving magnetic sensitivity.

Differential sensing with banked RRAM cells and current limiting improves read precision, redundancy, and array reliability.

A refresh control circuit selectively refreshes memory-bank subsets so other banks remain accessible, reducing downtime during refresh cycles.

An integrated resistor in the OTS cell absorbs snap-back current overshoot, extending cell lifetime without increasing area.

A vertically stacked capacitor increases storage-node capacitance in gain-cell RAM, limiting leakage effects and reducing refresh needs without expanding cell area.

A three-stage internal clock scheme cuts memory RC delay, access time, and toggle power while limiting buffer area in scaled nodes.

Leakage-prone canary cells signal impending failures, allowing embedded DRAM to lower refresh frequency while preserving data integrity.

One memory array switches between column-multiplexed access and wide-vector in-memory computation for faster, lower-power neural operations.

ECC-protected row counters detect activation thresholds and trigger targeted refreshes to limit row hammer data loss without excess refresh overhead.

Asymmetric write-error curves are addressed with state-specific pulse widths that improve STT-MRAM reliability while limiting repeat writes.

Overlapping driver circuits with memory blocks uses the vertical dimension to simplify routing and support a smaller memory layout.

Dynamic overdrive and steady-state voltages accelerate bitcell activation while limiting power use during normal reading.

A combined high-temperature anneal before MTJ etching sets magnetic domains and limits etch-byproduct redeposition.

Fluorinated substrate material lowers refractive index, increasing modulation while retaining monomer solubility in holographic media.

Crossing row outputs keep opposite wordlines non-aligned, reducing coupled discharges and data corruption during access.

Combining CNT and resistive memory parts around a shared electrode doubles density while reducing memory-cell volume.

A stepped MRAM top electrode separates contact width from MTJ support, reducing stress and preventing gaps in dense layouts.

AND and XNOR logic replace costly gating and scalar-product operations in near-memory binary neural networks, reducing power and area.

Dynamic reference-potential updates use differential strobe intermediate levels to preserve the data signal window during voltage and temperature changes.

Vertical via-holes protect selector and variable-resistance layers from redeposition and surface roughness in dense cross-point memory arrays.

Staggering self-refresh across bank subsets bounds peak current, easing PDN requirements while keeping every memory bank refreshed.

Selective field-line activation writes magnetic data with lower current while avoiding unnecessary parallel magnetic resistance and saturation.

Data retention information sets different refresh pulse counts for DRAM banks, reducing unnecessary refreshes, power use, and lost memory bandwidth.

Multilevel voltage levels let memory terminals carry more commands and addresses, reducing pin count, die size, and circuit complexity.

An asymmetric staggered source-drain layout compresses transistor area while vertical channels support denser memory cells.

Dynamic offset-cancellation timing uses voltage and temperature feedback to preserve DRAM sensing margins across PVT variation.

Multiple patterning forms word-line sections separately, lowering aspect ratios to prevent twisting or collapse in dense memory arrays.

Detect defective memory cells through word line leakage and voltage comparison, avoiding write/read cycles to save test time and power.

Reduced conductance values and access-transistor gate control help limit noise and energy dissipation while improving computational precision in crossbar memory.

Interleaved N-well and P-well pickups can cause implant aperture effects and latch-up; grouping them reduces boundaries and dose compensation.

Unequal rising and falling times shrink the data valid window; a de-skew buffer aligns complementary timing for more accurate reads.

Feedback-controlled load transistors strengthen the dual-tail latch voltage differential for low-voltage fidelity without added current sources.