DRAM Row Decoder Layout With Shared Block MUX Activation
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Solution Overview
Problem
Memory devices, such as DRAMs, face challenges with increased area and power consumption due to the need for a row decoder that includes the same number of block MUXs as row blocks, leading to inefficiencies.
Innovation Solution
Implement a row decoder with a row block select circuit that integrates block MUXs using continuity of row address coding, reducing the number of block MUXs and integrating them in the pad region, and using a row block select circuit to generate global MUX activation signals based on decoded row addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the row decoder includes the same number of block MUXs as row blocks, then each row block can be activated independently, but the area and power consumption of the row decoder increase significantly
Solution Approach 1:
Multiple block MUXs are merged into a single shared block MUX unit. The patent integrates several block MUX functions into one shared resource that can be dynamically controlled to serve multiple row blocks, thereby reducing the total number of block MUXs and decreasing the row decoder area while maintaining the capability to activate any row block independently through coordinated control signals
Solution Approach 2:
The shared block MUX is designed to perform multiple functions by serving different row blocks at different times. A single block MUX unit is configured to handle activation requests for multiple row blocks through time-multiplexed control, making it a universal component that replaces multiple dedicated block MUXs while preserving full row block activation capability
2Adaptability or versatility
If the row decoder includes the same number of block MUXs as row blocks, then each row block can be activated independently, but the power consumption of the row decoder increases significantly
Solution Approach 1:
Multiple block MUXs are merged into a single shared block MUX unit. The patent integrates several block MUX functions into one shared resource that can be dynamically controlled to serve multiple row blocks, thereby reducing the total number of block MUXs and decreasing the row decoder area while maintaining the capability to activate any row block independently through coordinated control signals
Solution Approach 2:
The shared block MUX is designed to perform multiple functions by serving different row blocks at different times. A single block MUX unit is configured to handle activation requests for multiple row blocks through time-multiplexed control, making it a universal component that replaces multiple dedicated block MUXs while preserving full row block activation capability
3Reliability
If the row decoder occupies a large area, then sufficient block MUXs can be provided for each row block, but unnecessary leakage current and signal skew occur
Solution Approach 1:
Multiple block MUXs are merged into a single shared block MUX unit. The patent integrates several block MUX functions into one shared resource that can be dynamically controlled to serve multiple row blocks, thereby reducing the total number of block MUXs and decreasing the row decoder area while maintaining the capability to activate any row block independently through coordinated control signals
Solution Approach 2:
The shared block MUX acts as an intermediary between the row decoder control logic and multiple row blocks. By introducing this single shared component that mediates activation requests to multiple row blocks, the patent reduces the number of direct connections and intermediate components needed, thereby reducing leakage current and signal skew while maintaining reliable signal transmission
Data Source
AI summary
A memory device according to an embodiment of the present disclosure may include a memory bank including a plurality of rows, a row decoder including a plurality of row blocks associated with the plurality of rows and configured to activate a specific row block of the plurality of row blocks based on a local row group address and a plurality of local MUX activation signals, an interface circuit configured to receive a global row group address, a plurality of global MUX activation signals, and a decoded bank address, generate the local row group address and the plurality of local MUX activation signals, and transmit the local row group address and the plurality of local MUX activation signals to the row decoder, and a row block select circuit configured to generate the global row group address and the plurality of global MUX activation signals based on a decoded row address.


