Subarray Memory Architecture for Dual-Mode Neural Computing
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Solution Overview
Problem
Existing memory architectures struggle to support both digital in-memory computation processing with wide vector access and conventional memory access while maintaining high processing speed and low power consumption, particularly in neural computing applications.
Innovation Solution
A memory array architecture that includes sub-arrays with a row decoder circuit and column multiplexing, allowing for both conventional memory access and digital in-memory computation modes, with error correction and safety features to ensure reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory architecture supports digital in-memory computation with wide vector access, then processing speed and computational efficiency are improved, but device complexity and power consumption increase
Solution Approach 1:
The memory architecture is designed to perform both conventional memory access operations and digital in-memory computation operations using the same physical memory array and circuitry. The row decoder circuit can operate in two modes: conventional mode for standard memory access and computation mode for wide vector access operations. This multi-functionality allows the system to achieve high processing speed for neural network operations without requiring separate dedicated computation hardware, thereby improving productivity while controlling device complexity.
2Productivity
If the memory architecture supports digital in-memory computation with wide vector access, then computational efficiency is improved, but power consumption increases
Solution Approach 1:
The memory array performs computation operations directly within its own structure without requiring data to be transferred to separate processing units. The local bit lines and row decoder circuits within the memory array itself execute the computation functions, allowing the memory system to serve both storage and computation needs. This self-service approach eliminates energy-consuming data transfer operations and achieves high computational efficiency while maintaining reasonable power consumption levels.
3Productivity
If the row decoder circuit simultaneously actuates one word line per sub-array during in-memory computation, then wide vector access is enabled, but circuit complexity increases
Solution Approach 1:
The memory array is divided into multiple sub-arrays, and the row decoder circuit is designed to independently control word lines in each sub-array. During in-memory computation operations, the row decoder can simultaneously actuate one word line per sub-array, enabling wide vector access across the entire memory array. This segmentation approach allows parallel operation across multiple sub-arrays, achieving high productivity while distributing the circuit complexity across modular units rather than requiring a single complex decoder.
4Reliability
If conventional memory access mode is used, then error correction and reliability are maintained, but processing speed for neural computing is reduced
Solution Approach 1:
The memory architecture implements dynamic mode switching capability, allowing the row decoder circuit to transition between conventional memory access mode and in-memory computation mode based on operational requirements. When reliability and error correction are prioritized, the system operates in conventional mode with full error correction protocols. When processing speed for neural computing is prioritized, the system switches to computation mode with wide vector access. This dynamic adaptability allows the system to optimize performance for different operational contexts without sacrificing either reliability or speed.
Data Source
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AI summary
A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports: a first mode where only one word line in the memory array is actuated during a column multiplexed memory access operation; and a second mode where one word line per sub-array is simultaneously actuated during an in-memory computation operation. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs to provide data read from the array in the first mode, and a sub-array data output coupled to each bit line input to provide weight data read from the array in the second mode. A computational circuit executes the in-memory computation as a function of feature data and the read weight data.