Bank-Specific Refresh Control Circuit for DRAM Retention
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Solution Overview
Problem
In dynamic random access memory (DRAM), uniform refresh frequencies lead to unnecessary refresh operations and increased power consumption due to varying data retention among memory cells, reducing memory access bandwidth.
Innovation Solution
A refresh control circuit that adjusts the pulse number or frequency of clock signals based on data retention information for individual memory banks, using components like pulse number adjusters, address counters, and gate control circuits to optimize refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform refresh frequency is adopted to refresh all memory cells, then all memory cells can be refreshed periodically, but many unnecessary refresh operations occur, reducing memory access bandwidth and increasing power consumption
Solution Approach 1:
The patent segments the memory banks into different groups based on their data retention characteristics. Each group is assigned a different refresh frequency, allowing memory banks with better data retention to be refreshed less frequently while those with poorer retention are refreshed more often. This segmentation resolves the contradiction by enabling differentiated refresh strategies that maintain reliability where needed while improving overall productivity.
Solution Approach 2:
The patent applies local quality by assigning different refresh frequencies to different memory bank groups according to their specific data retention needs. Instead of applying a uniform refresh frequency globally, each group receives a customized refresh rate tailored to its local characteristics, thereby eliminating unnecessary refresh operations in groups with good data retention while maintaining data integrity in groups that require more frequent refreshing.
2Reliability
If a uniform refresh frequency is adopted to refresh all memory cells, then all memory cells can be refreshed periodically, but unnecessary power consumption is increased
Solution Approach 1:
The patent segments memory banks into groups with different refresh frequencies based on their data retention characteristics. This segmentation allows the system to reduce power consumption by refreshing only the necessary groups at appropriate frequencies, rather than uniformly refreshing all memory banks regardless of their actual needs.
Solution Approach 2:
The patent applies local quality by tailoring the refresh frequency to the specific data retention needs of each memory bank group. Groups with good data retention are assigned lower refresh frequencies, reducing power consumption, while groups with poor retention receive higher frequencies to ensure data integrity. This localized approach optimizes the balance between reliability and energy efficiency.
3Productivity
If the pulse number of clock signal is adjusted according to data retention information, then refresh operation frequency can be optimized for each memory bank, but the device complexity increases
Solution Approach 1:
The patent merges the refresh control functionality into the existing clock signal distribution infrastructure. By using pulse number adjusters that modify the clock signal based on data retention information and integrating this with the address counter system, the patent achieves differentiated refresh control without adding completely separate control circuits for each memory bank, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent applies universality by designing the pulse number adjusters and address counter system to serve multiple memory bank groups simultaneously. A single address counter generates refresh addresses for multiple groups, and the pulse number adjustment mechanism uniformly applies different refresh rates across groups based on their retention characteristics. This multi-functional approach improves refresh efficiency while avoiding the complexity of completely independent control circuits for each bank.
Data Source
AI summary
A refresh control circuit includes a clock signal generator, a plurality of pulse number adjusters and a plurality of address counters. The clock signal generator generates a clock signal. The pulse number adjusters receive the clock signal, and during a time period, respectively generate a plurality of adjusted clock signals by adjusting pulse number of the clock signal according to a plurality of data retention information. The address counters respectively generate a plurality of refresh address information according to the adjusted clock signals. The refresh address information respectively correspond to a plurality of memory banks of a memory device. The memory banks respectively perform refresh operations according to the refresh address information.