FeFET Memory Structure With Conductive Spacers for Erase Switching
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Solution Overview
Problem
FeFET based memory devices, particularly those using oxide semiconductors, face challenges in achieving a uniform electric field across the ferroelectric layer due to insufficient hole carriers, leading to lower erase efficiency during polarization switching.
Innovation Solution
The integration of conductive spacers in the channel region of FeRAM devices, which provide additional hole carriers and enhance the coupling electric field in the ferroelectric layer, allowing for full polarization switching and improved erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductor is used as channel material in FeFET, then low power requirements and small size are achieved, but insufficient hole carriers result in non-uniform electric field and low erase efficiency
Solution Approach 1:
A conductive spacer layer is introduced as an intermediary component between the source/drain region and the channel region. This spacer layer serves as a mediator to provide additional hole carriers to the oxide semiconductor channel, enabling uniform electric field distribution across the ferroelectric layer and achieving full polarization switching during erase operations.
2Use of energy by moving object
If wide band gap oxide semiconductor is used, then low power consumption is achieved, but lack of sufficient hole carriers prevents full polarization switching
Solution Approach 1:
The conductive spacer layer acts as a mediator that supplies hole carriers to the oxide semiconductor channel without affecting its low power consumption characteristic. This allows the device to maintain energy efficiency while achieving reliable full polarization switching through the enhanced hole carrier concentration provided by the spacer.
3Reliability
If conventional FeFET structure is used, then simple structure is maintained, but non-uniform electric field causes lower erase efficiency
Solution Approach 1:
The conductive spacer layer is introduced as a relatively simple intermediary component that can be integrated into the existing FeFET structure using standard deposition techniques. This adds minimal structural complexity while significantly improving erase efficiency by providing the necessary hole carriers for uniform electric field distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced coupling electric field in the ferroelectric layer results in a wider memory window and increased erase efficiency, improving the performance of FeFET based memory devices.
Implementation Method 1
enhance the coupling electric field in the ferroelectric layer
Implementation Method 2
provide additional hole carriers to the channel layer
Implementation Method 3
full polarization switching in the ferroelectric layer
Data Source
AI summary
Various embodiments provide a memory device including a layer stack comprising alternating layers of a dielectric material and an electrically conductive material, a first oxide material having a first sidewall and a second sidewall, a first spacer layer in contact with the first sidewall of the first oxide material, the first spacer layer having a first conductivity type, a second spacer layer in contact with the second sidewall of the first oxide material, wherein the second spacer layer has the first conductivity type. The memory device includes a channel layer having a second conductivity type that is opposite to the first conductivity type, wherein the channel layer is in contact with the first oxide material, the first spacer layer, and the second spacer layer. The memory device includes a ferroelectric layer in contact with the channel layer and the alternating layers of the dielectric material and the electrically conductive material.