Vertical 2-Transistor Memory Cell With Shared Read/Write Line
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Solution Overview
Problem
Conventional volatile memory devices face challenges in increasing storage density due to physical limitations and fabrication constraints when shrinking memory cell size, leading to inefficiencies in power dissipation and operation.
Innovation Solution
A memory device with 2-transistor vertical memory cells utilizing a shared access line for both transistors, allowing for a smaller footprint and improved processing efficiency, and storing information in a floating-gate structure to overcome these limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is shrunk to increase storage density, then storage density is improved, but fabrication constraints and physical limitations worsen
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a vertical 3D configuration where transistors are stacked above each other. This dimensional change allows the memory cell to achieve smaller footprint area while maintaining functional integrity, thereby increasing storage density without being constrained by conventional planar fabrication limits.
Solution Approach 2:
The shared access line serves dual functionality by providing both word line and bit line connections to the memory cell. This multi-functionality reduces the total number of required access lines, simplifying the fabrication process and reducing routing complexity while enabling smaller memory cell dimensions.
2Quantity of substance
If memory cell size is shrunk to increase storage density, then storage density is improved, but power dissipation worsens
Solution Approach 1:
By stacking transistors vertically, the patent reduces the lateral distance that charge carriers must travel during read/write operations. This shortened transport path reduces resistive power losses while maintaining the same storage capacity, thereby improving power efficiency alongside increased density.
Solution Approach 2:
The shared access line merges the word line and bit line functions into a single conductive path. This consolidation reduces the total number of line interfaces and associated leakage currents, thereby reducing overall power dissipation while enabling higher density through smaller cell footprint.
3Ease of manufacture
If conventional memory cell structure is used, then fabrication is simpler, but storage density is limited
Solution Approach 1:
The patent employs vertical stacking of transistors to create a 3D memory cell structure. This approach increases storage density by utilizing the vertical dimension while maintaining compatibility with standard semiconductor fabrication processes, thus achieving high density without sacrificing manufacturability.
Solution Approach 2:
The shared access line provides multiple functions (word line and bit line connectivity) through a single structure, simplifying the fabrication process by reducing the number of patterning and deposition steps required compared to conventional separate line structures, while enabling higher density.
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line, a second data line, a conductive line, and a memory cell coupled to the first and second data lines. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the first and second data lines, and charge storage structure electrically separated from the first region. The second transistor includes a second region electrically separated from the first region, the second region electrically coupled to the charge storage structure and the second data line. The conductive line is electrically separated from the first and second channel regions. Part of the conductive line is spanning across part of the first region of the first transistor and part of the second region of the second transistor.