3D Memory Cell Layout With Shared Word Lines and Central Pad Region
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Solution Overview
Problem
Conventional semiconductor memory devices with two-dimensional memory cells face limitations in integration due to the area occupied by unit memory cells, hindering the development of high-capacity devices.
Innovation Solution
The implementation of three-dimensional semiconductor memory devices with memory cells stacked vertically, utilizing a substrate with alternating stacked regions and pad regions, interconnected by word lines and bit lines, and driven by sub-word line drivers, enhancing integration and reducing the area occupied by pad regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If two-dimensional memory cells are used to increase integration, then the area occupied by unit memory cells is reduced, but the degree of integration is still limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking, where multiple memory cell layers are vertically stacked on the substrate. This dimensional change allows memory cells to be arranged in multiple levels (first stacked region and second stacked region), significantly increasing the number of memory cells per unit area and overcoming the integration limits of planar designs.
2Device complexity
If pad regions are placed between stacked regions, then word line connections are simplified, but the area occupied by pad regions increases
Solution Approach 1:
The patent merges the pad region with the stacked regions by positioning the pad region between the first and second stacked regions rather than separating them. This integration allows the pad region to serve dual purposes: providing electrical connections for word lines while occupying minimal space between the stacked memory regions, thereby reducing the overall area requirement.
3Productivity
If multiple stacked regions are used to increase memory capacity, then integration density improves, but the number of word line connections increases
Solution Approach 1:
The patent implements a shared word line structure where the same word lines extend across both the first and second stacked regions. This multi-functional design allows a single set of word lines to address memory cells in multiple stacked regions, eliminating the need for separate word line sets for each region and reducing connection complexity while maintaining high memory capacity.
Data Source
AI summary
A semiconductor memory device including a substrate including a first stacked region, a second stacked region, and a pad region, the pad region being between the first stacked region and the second stacked region in a first horizontal direction, a plurality of word lines extending from the pad region toward each of the first stacked region and the second stacked region in the first horizontal direction and spaced apart from each other in a vertical direction, a plurality of bit lines extending in the vertical direction and spaced apart from each other in the first horizontal direction in each of the first stacked region and the second stacked region, and a plurality of memory cells interposed between the plurality of word lines and the plurality of bit lines in each of the first and second stacked regions may be provided.