DRAM Sense Amplifier Offset Cancellation with Dynamic Timing
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices experience undesirable offset noise in sense amplifiers due to variations in power supply voltages and process, voltage, and temperature changes, affecting sensing margins and operating characteristics.
Innovation Solution
A memory device with a voltage detection circuit and temperature sensor that adjusts the offset cancellation time of the sense amplifier based on detected voltage and temperature information, using a control circuit to vary the offset cancellation operation and reduce offset noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If offset cancellation operation is performed with fixed time interval, then device complexity is reduced, but sensing margin deteriorates due to PVT variations and power supply voltage changes
Solution Approach 1:
The offset cancellation time interval is made dynamic rather than fixed. The control circuit adjusts the time interval based on detected power supply voltage levels and temperature conditions, allowing the sense amplifier to adapt to PVT variations and maintain optimal sensing margin under different operating conditions.
Solution Approach 2:
The system implements feedback mechanisms where voltage detection circuits monitor power supply voltage levels and temperature sensors monitor thermal conditions. This feedback information is used by the control circuit to dynamically adjust the offset cancellation time interval, ensuring optimal performance across varying operating conditions.
2Reliability
If offset cancellation time interval is extended to compensate for low voltage conditions, then sensing margin is improved, but operation speed deteriorates
Solution Approach 1:
The offset cancellation time interval is dynamically adjusted based on real-time voltage detection. When power supply voltage is high, the time interval is shortened to maintain operation speed. When voltage drops below a threshold, the time interval is extended to ensure adequate offset cancellation and sensing margin, thus optimizing the trade-off between speed and reliability under different voltage conditions.
3Reliability
If offset cancellation operation is performed continuously, then offset noise is reduced, but power consumption increases
Solution Approach 1:
The offset cancellation operation is performed periodically rather than continuously. The control circuit determines appropriate time intervals based on voltage detection and temperature sensing, performing offset cancellation only when necessary to maintain sensing margin, thus reducing unnecessary power consumption while still effectively managing offset noise.
Data Source
AI summary
A method of operating a memory device includes precharging a pair of true and complementary bit lines (BL/BLB) to an equivalent voltage concurrently with precharging a pair of true and complementary sense bit lines (SABL/SABLB) to the equivalent voltage, and then transferring charge associated with offset noise from BL to SABLB concurrently with transferring charge associated with the offset noise from BLB to SABL, so that a voltage difference is established between the SABL and SABLB. Next, a logic state of a memory cell connected to BI is read by transferring charge between the memory cell and BL, concurrently with equilibrating voltages on SABL and SABLB. Then, a voltage difference between SABL and SABLB is sensed and amplified in response to activating an amplifier circuit within the sense amplifier.