Vertically Overlapped Memory Drivers for Compact 3D Layout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor memory product market is highly competitive, and reducing manufacturing costs is crucial for increasing profitability and market share, which can be achieved by minimizing the area required for implementation.
Innovation Solution
A memory device design with a stacked peripheral structure and memory array configuration, where memory-group-driver circuits overlap with memory blocks vertically, reducing the need for interconnect lines and optimizing the layout to minimize area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If peripheral circuits are arranged laterally adjacent to memory blocks, then circuit connectivity is simplified, but the overall device area increases
Solution Approach 1:
The patent transitions from lateral arrangement of peripheral circuits to vertical stacking above memory blocks. The peripheral structure is formed on a second substrate and stacked with the memory array structure, utilizing the vertical dimension to reduce lateral area while maintaining circuit connectivity through vertical interconnects.
Solution Approach 2:
The peripheral circuits are nested above the memory blocks in a vertical configuration. The peripheral structure containing driver circuits and interconnect lines is stacked within the same footprint as the memory array, effectively nesting functional elements in the vertical space rather than expanding laterally.
2Device complexity
If more interconnect lines are used to connect peripheral circuits, then circuit connectivity is improved, but the manufacturing cost and area increase
Solution Approach 1:
Instead of expanding interconnect lines laterally to connect peripheral circuits, the patent uses vertical interconnects to connect the stacked peripheral structure with the memory array. This dimensional change reduces the number of lateral interconnect lines required, simplifying manufacturing and reducing area.
3Productivity
If the chip area is reduced to minimize manufacturing cost, then profitability increases, but the complexity of layout and routing increases
Solution Approach 1:
The patent resolves layout complexity by moving to a three-dimensional stacked architecture. Peripheral circuits that would traditionally require complex lateral routing are instead positioned vertically above memory blocks, connected through vertical interconnects. This simplifies the lateral layout while maintaining full functionality.
Solution Approach 2:
The device is segmented into distinct functional layers: the memory array structure on the first substrate and the peripheral structure on the second substrate, which are then stacked and bonded. This segmentation allows independent optimization of each layer while reducing overall area through vertical integration.
Data Source
AI summary
A memory device includes a memory array structure having a plurality of memory banks, each memory bank including a plurality of memory groups, each memory group having at least one memory block; and a peripheral structure stacked with the memory array structure in a vertical direction, and having a plurality of memory-group-driver circuits each corresponding to one of the plurality of memory groups, respectively, wherein each memory-group-driver circuit is coupled with word lines of at least one memory block of a corresponding one of memory groups, and overlaps with one of the at least one memory blocks in the vertical direction. Each memory-group-driver circuit may include a precharge-voltage-driver circuit configured to provide a precharge voltage to the word lines, and a discharge-voltage-driver circuit configured to provide a discharge voltage to the word lines.