Near-Memory Binary Neural Network Circuit Using AND/XNOR Logic
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Solution Overview
Problem
Existing near-memory binary neural network architectures face challenges in terms of performance, power consumption, and area, particularly due to the computational expense of operators like scalar products and gating mechanisms, and the need to improve these aspects is evident.
Innovation Solution
A circuit is designed with a first and second memory element, a computing circuit, and logic gates to perform binary operations efficiently, utilizing specific read functions and multiplexers to generate output vectors, and a scheduler to control memory access, allowing for dynamic masking and modulation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional near-memory binary neural network architectures are used, then memory access efficiency is improved, but computational expense and power consumption increase due to operators like scalar products and gating mechanisms
Solution Approach 1:
The patent extracts the computationally expensive gating mechanisms (softmax, sigmoid functions and point-by-point multiplication) from the traditional near-memory architecture and replaces them with simplified binary operations. This extraction removes the harmful computational overhead while preserving the essential memory-efficient near-memory access pattern, thereby reducing power consumption without sacrificing memory access efficiency.
Solution Approach 2:
The patent employs simple binary logic operations (AND, XNOR) instead of complex floating-point arithmetic operations. These simple binary operations act as 'cheap' computational primitives that consume significantly less power while achieving the same functional outcome. The use of basic logic gates replaces expensive computational objects with inexpensive binary operations.
2Adaptability or versatility
If gating mechanisms with activation functions are implemented, then contextualization of processing is improved, but computational complexity and area increase
Solution Approach 1:
The patent changes the parameter space from continuous real numbers to discrete binary values. By transforming activation functions and gating mechanisms to operate in binary domain instead of continuous domain, the patent maintains contextualization capability through binary masking and selection operations while dramatically reducing computational complexity and hardware area requirements.
Solution Approach 2:
The patent substitutes complex mathematical mechanical systems (activation functions like softmax and sigmoid, point-by-point multiplication) with simple binary logic operations. This substitution replaces the mechanical computation of continuous functions with discrete logic gate operations, reducing device complexity while preserving the essential gating and contextualization functions.
3Device complexity
If arithmetic operations are standardized across all layers, then hardware simplicity is improved, but adaptability to different network requirements deteriorates
Solution Approach 1:
The patent creates a universal binary arithmetic framework that can handle multiple operation types (scalar products, gating mechanisms, activation functions) using the same basic binary logic operations. This multi-functional approach allows a single standardized hardware architecture to adapt to different network requirements through software-controlled operation selection rather than dedicated hardware for each operation type.
Solution Approach 2:
The patent introduces dynamic operation selection capability where the same binary logic hardware can dynamically switch between different arithmetic operations (AND for scalar products, XNOR for gating) based on control signals. This dynamic reconfigurability allows standardized hardware to adapt to different computational requirements of various network layers without increasing hardware complexity.
Data Source
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AI summary
This description concerns a circuit comprising: - a first memory element configured to store a data point; - a second memory element configured to store a weight matrix in association with a layer of a binary neural network; - a computing circuit configured to: a) receive the first data point and the k-th row of the weight matrix; b) receive a first control signal, indicating the nature of each of the first and second read functions, each associated with a two-valued arithmetic; c) generate a first vector by applying the first read function to the k-th row of the weight matrix and a second vector by applying the second read function to the data point; and d) generate a k-th component of a first output vector based on the first and second vectors.