Shared Page Buffer Layout for Compact Non-Volatile Memory
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Solution Overview
Problem
As non-volatile memory devices increase in capacity and miniaturization, the area of the peripheral circuit region remains significant, hindering further reduction in size due to the need for separate peripheral circuits for each memory cell array.
Innovation Solution
Implementing a shared page buffer circuit for multiple memory cell arrays, reducing the need for duplicate peripheral circuits and allowing for a more compact design by integrating the peripheral circuit with the memory cell arrays in a vertical structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate peripheral circuits are provided for each memory cell array to ensure independent operation and reliability, then the operational reliability is improved, but the area of the peripheral circuit region increases, hindering miniaturization
Solution Approach 1:
The patent merges the page buffer circuits from multiple memory cell arrays into a single shared page buffer circuit. Specifically, first and second memory cell arrays that previously had separate page buffers now share a common page buffer circuit, reducing the total peripheral circuit area while maintaining the ability to independently operate each memory cell array through selective connection mechanisms.
Solution Approach 2:
The shared page buffer circuit is designed to serve multiple memory cell arrays simultaneously. The circuit incorporates switching mechanisms that allow it to connect to and operate with different memory cell arrays as needed, providing universal functionality that replaces multiple dedicated circuits with a single multi-functional unit.
2Quantity of substance
If the number of word lines stacked on substrate is increased to increase memory capacity, then the storage capacity is improved, but the area of the cell region decreases due to vertical stacking constraints
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical stacking architecture. Multiple word lines are stacked vertically on the substrate, allowing memory capacity to increase along the vertical dimension rather than requiring proportional increases in horizontal cell region area. This dimensional change enables higher density storage.
3Area of stationary object
If a shared page buffer circuit is implemented for multiple memory cell arrays to reduce peripheral circuit area, then the device miniaturization is improved, but the device complexity increases due to switching and connection management
Solution Approach 1:
The patent introduces switching circuits as intermediary components that manage connections between the shared page buffer circuit and multiple memory cell arrays. These switches act as mediators that simplify the connection management by providing controlled access paths, reducing the complexity of directly managing multiple simultaneous connections without the shared buffer.
Data Source
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AI summary
A non-volatile memory device includes a first semiconductor layer including a first cell region in which a first memory cell array is disposed, a second cell region in which a second memory cell array is disposed, , wherein the first memory cell array and the second memory cell array each include a plurality of word lines, a plurality of memory cells, and a plurality of bit lines, and a second semiconductor layer including a page buffer circuit region in which a page buffer circuit connected to the first memory cell array and the second memory cell array is disposed, , wherein the page buffer circuit region overlaps a boundary region between the first cell region and the second cell region when viewed from the vertical direction.