Gain-Cell RAM with Vertically Integrated Capacitor for Charge Retention
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Solution Overview
Problem
GCRAM cells suffer from low charge retention due to low capacitance at the storage node and leakage currents, which are exacerbated by the need for refresh circuits that increase space and power consumption.
Innovation Solution
Introduce a capacitor vertically stacked with the read and write transistors, coupled to the storage node in parallel with the gate dielectric, to enhance capacitance and reduce leakage effects, maintaining charge retention without increasing footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is added to increase capacitance at the storage node, then charge retention is improved, but device area increases
Solution Approach 1:
The capacitor is nested within the existing transistor structure by utilizing the transistor body as part of the capacitor structure. The capacitor's first electrode is formed using the transistor source/drain region, and the second electrode is formed using the transistor gate, with the gate dielectric serving as the capacitor dielectric. This nesting approach allows the capacitor to be integrated without adding external area.
Solution Approach 2:
The transistor structure serves dual functions: it acts as both the switching device and as part of the capacitor structure. The transistor's gate dielectric, source/drain regions, and channel are utilized to form the capacitor's electrodes and dielectric, making the transistor structure multi-functional rather than requiring separate dedicated capacitor components.
2Reliability
If refresh circuits are added to compensate for leakage, then charge retention is improved, but power consumption and area increase
Solution Approach 1:
The patent eliminates the need for expensive and complex refresh circuits by using a simpler, permanent capacitor structure that passively maintains charge. The capacitor provides continuous charge retention without requiring active refresh operations, effectively replacing the need for periodic refreshing mechanisms.
3Reliability
If the capacitor is made larger to increase capacitance, then charge retention is improved, but manufacturing complexity increases
Solution Approach 1:
The capacitor structure is merged with the transistor fabrication process. The same deposition, etching, and processing steps used to create the transistor are used to form the capacitor's electrodes and dielectric layers. This merging eliminates the need for separate capacitor manufacturing steps and simplifies the overall fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitor increases charge retention by over 100 times, reduces the need for refresh circuits, and lowers power consumption, while maintaining a compact memory cell size.
Implementation Method 1
a capacitor spaced from the first read transistor and the write transistor and further separated from the substrate by the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node
Data Source
AI summary
Some embodiments relate to a memory cell, including: a write transistor on a substrate and comprising a first gate terminal, a first source/drain region, and a second source/drain region coupled to a storage node; a first read transistor on the substrate and comprising a second gate terminal coupled to the storage node and a gate dielectric with a first capacitance; and a capacitor spaced from the first read transistor and the write transistor and further separated from the substrate by the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node and has a second capacitance that is over twice the first capacitance.