Three-Dimensional Memory Array Patterning for Stable Word Lines
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving high memory cell density while preventing structural instability due to high aspect ratios during the formation of word lines and bit lines, leading to issues such as twisting or collapsing of features.
Innovation Solution
A multiple-patterning process is employed to form word lines and transistors, where first and second subsets are formed in separate patterning processes, reducing the aspect ratio and minimizing defects, thereby improving the stability and density of the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional single-patterning process is used to form word lines and bit lines, then manufacturing process is simpler, but high aspect ratios cause structural instability leading to twisting or collapsing of features
Solution Approach 1:
The patent divides the single patterning process into multiple sequential patterning steps. First, a mandrel layer is formed and patterned, then a first conformal layer is deposited and patterned, followed by a second conformal layer deposition and patterning. This segmentation allows each step to work with lower aspect ratios, preventing structural collapse while achieving the final high-density interconnect structure.
Solution Approach 2:
The patent employs preliminary actions by forming sacrificial mandrels and using conformal deposition techniques before final patterning. The mandrels are formed first to define the structure, then conformal layers are deposited to build up the interconnect structure in a controlled manner, ensuring structural stability is maintained throughout the process.
2Quantity of substance
If memory cell density is increased, then storage capacity is improved, but aspect ratio increases causing structural instability and defects
Solution Approach 1:
The patent transitions from planar patterning to three-dimensional conformal deposition. By depositing layers conformally over the substrate and previous layers, the process builds structure in the vertical dimension while maintaining controlled aspect ratios at each step, thereby increasing memory cell density without compromising structural stability.
Solution Approach 2:
The patent segments the density enhancement into multiple deposition and patterning cycles. Each cycle adds another layer of interconnect structure, progressively increasing capacity while maintaining manageable aspect ratios through the sequential nature of the process.
3Reliability
If multiple-patterning process is used to form word lines and transistors in separate processes, then aspect ratio is reduced and defects are minimized, but manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple patterning operations into an integrated process flow. The mandrel formation, first conformal layer deposition and patterning, and second conformal layer deposition and patterning are combined into a unified manufacturing sequence, reducing process complexity while maintaining the reliability benefits of multiple patterning steps.
Data Source
AI summary
A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.