Via-Hole Selector Structure for Cross-Point Memory Integrity
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Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining the performance and integrity of memory cells due to manufacturing defects and material deterioration during patterning processes, particularly in high-density cross-point arrays where the selector and variable resistance layers are sensitive to redeposition and surface roughness.
Innovation Solution
The formation of a selector layer perpendicular to the substrate and conductive lines in a via hole structure prevents material redeposition and surface roughness, ensuring the integrity of the selector and variable resistance layers by controlling access and reducing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar patterning processes are used to form memory cells in high-density cross-point arrays, then manufacturing complexity is reduced, but material redeposition and surface roughness occur during patterning, causing manufacturing defects and performance degradation
Solution Approach 1:
The patent transitions from conventional planar (2D) patterning to a vertical (3D) via-hole structure. The selector layer is formed as a vertical columnar structure within via-holes, perpendicular to the substrate, rather than as a planar layer. This dimensional change eliminates material redeposition on the selector layer surface during patterning processes, as the vertical configuration prevents horizontal material flow onto the selector layer, thereby maintaining manufacturing precision while managing complexity.
Solution Approach 2:
The patent introduces an intermediary electrode layer positioned between the selector layer and the variable resistance layer. This electrode layer acts as a protective barrier that prevents material redeposition from reaching the selector layer during subsequent patterning and deposition processes. The intermediary layer absorbs the harmful effect of material redeposition, protecting the selector layer integrity while allowing the manufacturing process to proceed.
2Quantity of substance
If high-density cross-point arrays are manufactured using conventional processes, then device capacity increases, but manufacturing defects and material deterioration increase, reducing device reliability
Solution Approach 1:
The vertical via-hole structure enables higher memory cell density by utilizing the third dimension (vertical space) for cell formation. Multiple via-holes can be densely packed in the planar direction while maintaining adequate spacing, and the vertical extent of the via-holes provides additional functional layers (selector layer, electrode layers, variable resistance layers) without increasing planar footprint. This dimensional approach maintains reliability by preventing material deterioration while achieving high density.
Solution Approach 2:
The patent applies different material compositions and structural configurations to specific regions of the memory cell to optimize local performance. The selector layer uses specific materials with desired electrical characteristics, the electrode layers use conductive materials optimized for their interface functions, and the variable resistance layer uses materials tailored for resistive switching. This local optimization ensures each component performs reliably while contributing to overall high-density array functionality.
Data Source
AI summary
A semiconductor device may include: a first conductive line including an opening passing through the first conductive line; a second conductive line disposed over the first conductive line and spaced apart from the first conductive line; a first electrode layer buried in the opening; a selector layer disposed in the opening and surrounding side surfaces of the first electrode layer; and a variable resistance layer disposed over the selector layer and the first electrode layer.